Primitive: Carry Look-Ahead Multiplexer
- PRIMITIVE_GROUP: CLB
- PRIMITIVE_SUBGROUP: CARRY
Introduction
Carry look-ahead multiplexer.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| CIN | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| COUTB | Output | 1 | Output of Carry Look-Ahead multiplexer. |
| COUTD | Output | 1 | Output of Carry Look-Ahead multiplexer. |
| COUTF | Output | 1 | Output of Carry Look-Ahead multiplexer. |
| COUTH | Output | 1 | Output of Carry Look-Ahead multiplexer. |
| CYA | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| CYB | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| CYC | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| CYD | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| CYE | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| CYF | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| CYG | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| CYH | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| PROPA | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| PROPB | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| PROPC | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| PROPD | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| PROPE | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| PROPF | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| PROPG | Input | 1 | Input of Carry Look-Ahead multiplexer. |
| PROPH | Input | 1 | Input of Carry Look-Ahead multiplexer. |
Design Entry Method
| Instantiation | Yes |
| Inference | Recommended |
| IP and IP Integrator Catalog | Yes |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| LOOKB | STRING | "FALSE", "TRUE" | "FALSE" | If TRUE, enable LOOKAHEAD to bring carry results from last stage. |
| LOOKD | STRING | "FALSE", "TRUE" | "FALSE" | If TRUE, enable LOOKAHEAD to bring carry results from last stage. |
| LOOKF | STRING | "FALSE", "TRUE" | "FALSE" | If TRUE, enable LOOKAHEAD to bring carry results from last stage. |
| LOOKH | STRING | "FALSE", "TRUE" | "FALSE" | If TRUE, enable LOOKAHEAD to bring carry results from last stage. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LOOKAHEAD8: Carry Look-Ahead Multiplexer
-- Versal Prime series
-- Xilinx HDL Language Template, version 2021.1
LOOKAHEAD8_inst : LOOKAHEAD8
generic map (
LOOKB => "FALSE", -- (FALSE, TRUE)
LOOKD => "FALSE", -- (FALSE, TRUE)
LOOKF => "FALSE", -- (FALSE, TRUE)
LOOKH => "FALSE" -- (FALSE, TRUE)
)
port map (
COUTB => COUTB, -- 1-bit output: Output of Carry Look-Ahead mux
COUTD => COUTD, -- 1-bit output: Output of Carry Look-Ahead mux
COUTF => COUTF, -- 1-bit output: Output of Carry Look-Ahead mux
COUTH => COUTH, -- 1-bit output: Output of Carry Look-Ahead mux
CIN => CIN, -- 1-bit input: Input of Carry Look-Ahead mux
CYA => CYA, -- 1-bit input: Input of Carry Look-Ahead mux
CYB => CYB, -- 1-bit input: Input of Carry Look-Ahead mux
CYC => CYC, -- 1-bit input: Input of Carry Look-Ahead mux
CYD => CYD, -- 1-bit input: Input of Carry Look-Ahead mux
CYE => CYE, -- 1-bit input: Input of Carry Look-Ahead mux
CYF => CYF, -- 1-bit input: Input of Carry Look-Ahead mux
CYG => CYG, -- 1-bit input: Input of Carry Look-Ahead mux
CYH => CYH, -- 1-bit input: Input of Carry Look-Ahead mux
PROPA => PROPA, -- 1-bit input: Input of Carry Look-Ahead mux
PROPB => PROPB, -- 1-bit input: Input of Carry Look-Ahead mux
PROPC => PROPC, -- 1-bit input: Input of Carry Look-Ahead mux
PROPD => PROPD, -- 1-bit input: Input of Carry Look-Ahead mux
PROPE => PROPE, -- 1-bit input: Input of Carry Look-Ahead mux
PROPF => PROPF, -- 1-bit input: Input of Carry Look-Ahead mux
PROPG => PROPG, -- 1-bit input: Input of Carry Look-Ahead mux
PROPH => PROPH -- 1-bit input: Input of Carry Look-Ahead mux
);
-- End of LOOKAHEAD8_inst instantiation
Verilog Instantiation Template
// LOOKAHEAD8: Carry Look-Ahead Multiplexer
// Versal Prime series
// Xilinx HDL Language Template, version 2021.1
LOOKAHEAD8 #(
.LOOKB("FALSE"), // (FALSE, TRUE)
.LOOKD("FALSE"), // (FALSE, TRUE)
.LOOKF("FALSE"), // (FALSE, TRUE)
.LOOKH("FALSE") // (FALSE, TRUE)
)
LOOKAHEAD8_inst (
.COUTB(COUTB), // 1-bit output: Output of Carry Look-Ahead mux
.COUTD(COUTD), // 1-bit output: Output of Carry Look-Ahead mux
.COUTF(COUTF), // 1-bit output: Output of Carry Look-Ahead mux
.COUTH(COUTH), // 1-bit output: Output of Carry Look-Ahead mux
.CIN(CIN), // 1-bit input: Input of Carry Look-Ahead mux
.CYA(CYA), // 1-bit input: Input of Carry Look-Ahead mux
.CYB(CYB), // 1-bit input: Input of Carry Look-Ahead mux
.CYC(CYC), // 1-bit input: Input of Carry Look-Ahead mux
.CYD(CYD), // 1-bit input: Input of Carry Look-Ahead mux
.CYE(CYE), // 1-bit input: Input of Carry Look-Ahead mux
.CYF(CYF), // 1-bit input: Input of Carry Look-Ahead mux
.CYG(CYG), // 1-bit input: Input of Carry Look-Ahead mux
.CYH(CYH), // 1-bit input: Input of Carry Look-Ahead mux
.PROPA(PROPA), // 1-bit input: Input of Carry Look-Ahead mux
.PROPB(PROPB), // 1-bit input: Input of Carry Look-Ahead mux
.PROPC(PROPC), // 1-bit input: Input of Carry Look-Ahead mux
.PROPD(PROPD), // 1-bit input: Input of Carry Look-Ahead mux
.PROPE(PROPE), // 1-bit input: Input of Carry Look-Ahead mux
.PROPF(PROPF), // 1-bit input: Input of Carry Look-Ahead mux
.PROPG(PROPG), // 1-bit input: Input of Carry Look-Ahead mux
.PROPH(PROPH) // 1-bit input: Input of Carry Look-Ahead mux
);
// End of LOOKAHEAD8_inst instantiation
Related Information
- Versal ACAP Configurable Logic Block Architecture Manual (AM005)