DSPFP32 - 2021.1 English

Primitive: The DSPFP32 consists of a floating-point multiplier and a floating-point adder with separate outputs.

PRIMITIVE_GROUP: ARITHMETIC
PRIMITIVE_SUBGROUP: DSP

Introduction

The DSPFP32 consists of a floating-point multiplier and a floating-point adder that allows multiply-add, multiply-accumulate and independent multiply and multiply add. Each floating-point multiplier input can be IEEE binary32 (FP32 or single precision) or IEEE binary16 (FP16 or half precision) format. The floating-point adder only accepts binary32 inputs. Outputs are always in FP32 or single precision format.

Port Descriptions

Port	Direction	Width	Function
Cascade: Cascade Ports
ACIN_EXP<7:0>	Input	8	Cascaded A exponent data input from ACOUT_EXP of previous DSPFP32. If not used, tie port to all zeros.
ACIN_MAN<22:0>	Input	23	Cascaded A mantissa data input from ACOUT_MAN of previous DSPFP32. If not used, tie port to all zeros.
ACIN_SIGN	Input	1	Cascaded A sign data input from ACOUT_SIGN of previous DSPFP32. If not used, tie port to zero.
ACOUT_EXP<7:0>	Output	8	Cascaded A exponent data output.
ACOUT_MAN<22:0>	Output	23	Cascaded A mantissa data output.
ACOUT_SIGN	Output	1	Cascaded A sign data output.
BCIN_EXP<7:0>	Input	8	Cascaded B exponent data input from BCOUT_EXP of previous DSPFP32. If not used, tie port to all zeros.
BCIN_MAN<22:0>	Input	23	Cascaded B mantissa data input from BCOUT_MAN of previous DSPFP32. If not used, tie port to all zeros.
BCIN_SIGN	Input	1	Cascaded B sign data output.
BCOUT_EXP<7:0>	Output	8	Cascaded B exponent data output. Output is dependent on BCASCSEL.
BCOUT_MAN<22:0>	Output	23	Cascaded B mantissa data output. Output is dependent on BCASCSEL.
BCOUT_SIGN	Output	1	Cascaded B sign data output. Output is dependent on BCASCSEL.
PCIN<31:0>	Input	32	Cascaded data input from PCOUT of previous DSPFP32 to adder. If used, connect to PCOUT of upstream cascaded DSPFP32. If not used, tie port to all zeros.
PCOUT<31:0>	Output	32	Cascaded data output to PCIN of next DSPFP32. If used, connect to PCIN of downstream cascaded DSPFP32. Output is either FPM (PCOUTSEL=FPM) or FPA(PCOUTSEL=FPA). If not used, leave unconnected.
Control: Control Inputs/Status Bits
CLK	Input	1	This port is the DSP58 input clock, common to all internal registers and flip-flops.
FPINMODE	Input	1	Controls select for B/D input data mux. B is selected when FPINMODE=1, D is selected when FPINMODE=0.
FPOPMODE<6:0>	Input	7	Selects P0(FPOPMODE[1:0]) and P1(FPOPMODE[4:2]) input signals to the floating-point adder. Selects whether to invert P0(FPOPMODE[5]) or P1(FPOPMODE[6]) inputs to the adder.
Data: Data Ports
A_EXP<7:0>	Input	8	8-bit A data exponent. When using B16 data type, connect to (A_EXP[4:0]) and tie (A_EXP[7:5]) to zero.
A_MAN<22:0>	Input	23	23-bit A data mantissa. When using B16 data type, connect to (A_MAN[22:13]) and tie (A_EXP[12:0]) to zero.
A_SIGN	Input	1	A data sign bit.
B_EXP<7:0>	Input	8	8-bit B data exponent. When using B16 data type, connect to (B_EXP[4:0]) and tie (B_EXP[7:5]) to zero.
B_MAN<22:0>	Input	23	23-bit B data mantissa. When using B16 data type, connect to (B_MAN[22:13]) and tie (B_EXP[12:0]) to zero.
B_SIGN	Input	1	B data sign bit.
C<31:0>	Input	32	C data input in Binary32 format.
D_EXP<7:0>	Input	8	8 bit D data exponent. When using B16 data type, connect to (D_EXP[4:0]) and tie (D_EXP[7:5]) to zero.
D_MAN<22:0>	Input	23	23 bit D data mantissa. When using B16 data type, connect to (D_MAN[22:13]) and tie (D_EXP[12:0]) to zero.
D_SIGN	Input	1	D data sign bit.
FPA_INVALID	Output	1	Active-High, output signal indicating NaN for the adder/accumlator output.
FPA_OUT<31:0>	Output	32	Adder/accumlator data output in Binary32 format.
FPA_OVERFLOW	Output	1	Active-High, indicates largest finite number has been exceeded allowable in Binary32 format for the adder/accumulator output.
FPA_UNDERFLOW	Output	1	Active-High, indicates a tiny non-zero result has been detected on the adder/accumulator output.
FPM_INVALID	Output	1	Active-High, output signal indicating NaN for the multiplier output.
FPM_OUT<31:0>	Output	32	Multiplier data output in Binary32 format.
FPM_OVERFLOW	Output	1	Active-High, indicates largest finite number has been exceeded allowable in Binary32 format for the multiplier output.
FPM_UNDERFLOW	Output	1	Active-High, indicates a tiny non-zero result has been detected on the multiplier output.
Reset/Clock Enable: Reset/Clock Enable Inputs
ASYNC_RST	Input	1	Asynchronous reset for all registers. Input is only valid when RESET_MODE=ASYNC.
CEA1	Input	1	Active-High, clock enable for the first A (input) register. This port is only used if AREG=2 or INMODE0 = 1. When two registers are used, this is the first sequentially. When Dynamic AB Access is used, this clock enable is applied for INMODE[0]=1. If the A port is not used, tie Low.
CEA2	Input	1	Active-High, clock enable for the second A (input) register. When two registers are used, this is the second sequentially. When one register is used (AREG=1), CEA2 is the clock enable. If the A port is not used, tie Low.
CEB	Input	1	Active-High, clock enable for the B (input) register. If the B port (collectively B_SIGN, B_EXP, B_MAN) is not used, tie Low.
CEC	Input	1	Active-High, clock enable for the C (input) register (FPCREG>0). If the C port is not used, tie Low.
CED	Input	1	Active-High, clock enable for the D (input) registers (FPDREG=1). If the D port (collectively D_SIGN, D_EXP, D_MAN) is not used, tie Low.
CEFPA	Input	1	Active-High, clock enable for the FPA_PREG (output) registers (FPA_PREG=1). If register is not used, tie Low.
CEFPINMODE	Input	1	Active-High, clock enable for the FPINMODE (input) registers (INMODEREG=1). If register is not used, tie Low.
CEFPM	Input	1	Active-High, clock enable for FPM (output) register (FPM_PREG=1). If register is not used, tie Low.
CEFPMPIPE	Input	1	Active-High, clock enable for FPMPIPE post multiplier register (FPMPIPEREG=1). If register is not used tie Low.
CEFPOPMODE	Input	1	Active-High, clock enable for FPOPMODE post multiplier register (FPOPMODE>0). If register is not used, tie Low.
RSTA	Input	1	Reset for both A (input) registers (AREG=1 or 2). Polarity is determined by the IS_RSTA_INVERTED attribute. Tie to logic zero if port A is not used.
RSTB	Input	1	Reset for B (input) registers (FPBREG=1). Polarity is determined by the IS_RSTB_INVERTED attribute. Tie to logic zero if B port is not used.
RSTC	Input	1	Reset for the C (input) registers (FPCREG>0). Polarity is determined by the IS_RSTC_INVERTED attribute. Tie to logic zero if C port is not used.
RSTD	Input	1	Reset for the D (input) register. Polarity is determined by the IS_RSTD_INVERTED attribute. Tie to logic zero if D port is not used.
RSTFPA	Input	1	Reset for the FPA output register (FPA_PREG=1). Polarity is determined by the IS_RSTFPA_INVERTED attribute. Tie to logic zero if FPA port is not used.
RSTFPINMODE	Input	1	Reset for the FPINMODE (control input) register (INMODEREG=1). Polarity is determined by the IS_RSTFPINMODE_INVERTED attribute. Tie to logic zero if not used.
RSTFPM	Input	1	Reset for the FPM output register (FPM_PREG=1). Polarity is determined by the IS_RSTFPM_INVERTED attribute. Tie to logic zero if FPM port is not used.
RSTFPMPIPE	Input	1	Reset for the FPMPIPE register (FPMPIPEREG=1). Polarity is determined by the IS_RSTFPMPIPE_INVERTED attribute. Tie to logic zero if FPMPIPEREG=0.
RSTFPOPMODE	Input	1	Reset for the FPOPMODE (control input) registers (FPOPMREG>0). Polarity is determined by the IS_RSTFPOPMODE_INVERTED attribute. Tie to logic zero if FPOPMREG=0.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	Yes

Available Attributes

Attribute	Type	Allowed Values	Default	Description
Feature Control Attributes: Specifies how to use a given input data port (i.e., from general fabric, "DIRECT", or from another DSPFP32, "CASCADE").
A_FPTYPE	STRING	"B32", "B16"	"B32"	Selects floating-point data type for A. B16 is for binary16 (half-precision) and B32 is for binary32 (single-precision).
A_INPUT	STRING	"DIRECT", "CASCADE"	"DIRECT"	Selects the input to the A port between direct input ("DIRECT") or the cascaded input from the previous DSPFP32 ("CASCADE"). When set to CASCADE, A_FPTYPE must match on the two cascaded DSPFP32 slices.
BCASCSEL	STRING	"B", "D"	"B"	Selects either B or D data to output through BCOUT.
B_D_FPTYPE	STRING	"B32", "B16"	"B32"	Selects floating-point data type for B and D. B16 is for binary16 (half-precision) and B32 is for binary32 (single-precision). Note: When set to B16, D must be multiplied by A=1 before it can be used for binary32 addition.
B_INPUT	STRING	"DIRECT", "CASCADE"	"DIRECT"	Selects the input to the B port between parallel input ("DIRECT") or the cascaded input from the previous DSPFP32 ("CASCADE").
PCOUTSEL	STRING	"FPA", "FPM"	"FPA"	Select to output either multiplier output FPM or adder output FPA on the PCOUT output cascade of DSPFP32
USE_MULT	STRING	"MULTIPLY", "DYNAMIC", "NONE"	"MULTIPLY"	Selects usage of the multiplier. "MULTIPLY": Multiplier is being used. "NONE": Saves power when using only the Adder/Logic Unit.
Programmable Inversion Attributes: Specifies whether or not to use the optional inversions on specific pins for this component to change the active polarity of the pin function. When set to 1 on a clock pin (CLK), this component clocks on the negative edge. When set to 1 on other pins, it changes the function to behave active-Low rather than active-High. For pins that are buses, the bit-width of this attribute should match that of the bit-width of the associated pins and a binary value specifies which inverters to use and which to bypass. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the input polarity.
IS_ASYNC_RST_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the ASYNC_RST pin of this component. The default 1'b0 indicates that ASYNC_RST is not inverted.
IS_CLK_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the CLK pin of this component. The default 1'b0 indicates that CLK is not inverted.
IS_FPINMODE_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the FPINMODE pin of this component. The default 1'b0 indicates that the FPINMODE input is not inverted.
IS_FPOPMODE_INVERTED	BINARY	7'b0000000 to 7'b1111111	7'b0000000	Specifies whether or not to use the optional inversions on the individual FPOPMODE pins of this component. The default 6'b000000 indicates that all bits of the FPOPMODE bus are not inverted. Each bit controls its respective bit of the FPOPMODE bus.
IS_RSTA_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the RSTA pin of this component. The default 1'b0 indicates that RSTA is not inverted.
IS_RSTB_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the RSTB pin of this component. The default 1'b0 indicates that RSTB is not inverted.
IS_RSTC_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the RSTC pin of this component. The default 1'b0 indicates that RSTC is not inverted.
IS_RSTD_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the RSTD pin of this component. The default 1'b0 indicates that RSTD is not inverted.
IS_RSTFPA_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the RSTFPA pin of this component. The default 1'b0 indicates that RSTFPA is not inverted.
IS_RSTFPINMODE_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the RSTFPINMODE pin of this component. The default 1'b0 indicates that RSTFPINMODE is not inverted.
IS_RSTFPM_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the RSTFPM pin of this component. The default 1'b0 indicates that RSTFPM is not inverted.
IS_RSTFPMPIPE_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the RSTFPMPIPE pin of this component. The default 1'b0 indicates that RSTFPMPIPE is not inverted.
IS_RSTFPOPMODE_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the RSTFPOPMODE pin of this component. The default 1'b0 indicates that RSTFPOPMODE is not inverted.
Register Control Attributes: Pipeline Register Configuration/Specification
ACASCREG	DECIMAL	1, 0, 2	1	In conjunction with AREG, selects the number of A input registers on the A cascade path, ACOUT. This attribute must be equal to or one less than the AREG value: AREG=0: ACASCREG must be 0. AREG=1: ACASCREG must be 1. AREG=2: ACASCREG can be 1 or 2.
AREG	DECIMAL	1, 0, 2	1	Selects the number of A input pipeline registers. If A port is not in use, set to 1.
FPA_PREG	DECIMAL	1, 0	1	Select the number of registers to include for FPA output path. If FPA port is not in use, set to 1.
FPBREG	DECIMAL	1, 0	1	Selects the number of input registers for all B inputs (B_MAN, B_EXP and B_SIGN). If B ports are not in use, set to 1.
FPCREG	DECIMAL	3, 0, 1, 2	3	Selects the number of input registers for the C input. If C port is not in use, set to 1.
FPDREG	DECIMAL	1, 0	1	Selects the number of input registers for all D inputs (D_MAN, D_EXP and D_SIGN). If D ports are not in use, set to 1.
FPMPIPEREG	DECIMAL	1, 0	1	Select to add an additional pipeline register stage in the floating-point multiply.
FPM_PREG	DECIMAL	1, 0	1	Select the number of registers to include for FPM output path. If FPM port is not in use, set to 1.
FPOPMREG	DECIMAL	3, 0, 1, 2	3	Add internal register stages to the FPOPMODE input before it is used in the adder. If FPOPMODE port is not in use, set to 1.
INMODEREG	DECIMAL	1, 0	1	Add internal pipeline stages to the FPINMODE input.
RESET_MODE	STRING	"SYNC", "ASYNC"	"SYNC"	Selects if the enabled registers in the DSP are reset by their register specific synchronous resets (SYNC) or the common ASYNC_RST (ASYNC).

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- DSPFP32: The DSPFP32 consists of a floating-point multiplier and a floating-point adder  with separate outputs.
--          Versal Prime series
-- Xilinx HDL Language Template, version 2021.1

DSPFP32_inst : DSPFP32
generic map (
   -- Feature Control Attributes: Data Path Selection
   A_FPTYPE => "B32",                 -- B16, B32
   A_INPUT => "DIRECT",               -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
   BCASCSEL => "B",                   -- Selects B cascade out data (B, D).
   B_D_FPTYPE => "B32",               -- B16, B32
   B_INPUT => "DIRECT",               -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
   PCOUTSEL => "FPA",                 -- Select PCOUT output cascade of DSPFP32 (FPA, FPM)
   USE_MULT => "MULTIPLY",            -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE)
   -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
   IS_CLK_INVERTED => '0',            -- Optional inversion for CLK
   IS_FPINMODE_INVERTED => '0',       -- Optional inversion for FPINMODE
   IS_FPOPMODE_INVERTED => "0000000", -- Optional inversion for FPOPMODE
   IS_RSTA_INVERTED => '0',           -- Optional inversion for RSTA
   IS_RSTB_INVERTED => '0',           -- Optional inversion for RSTB
   IS_RSTC_INVERTED => '0',           -- Optional inversion for RSTC
   IS_RSTD_INVERTED => '0',           -- Optional inversion for RSTD
   IS_RSTFPA_INVERTED => '0',         -- Optional inversion for RSTFPA
   IS_RSTFPINMODE_INVERTED => '0',    -- Optional inversion for RSTFPINMODE
   IS_RSTFPMPIPE_INVERTED => '0',     -- Optional inversion for RSTFPMPIPE
   IS_RSTFPM_INVERTED => '0',         -- Optional inversion for RSTFPM
   IS_RSTFPOPMODE_INVERTED => '0',    -- Optional inversion for RSTFPOPMODE
   -- Register Control Attributes: Pipeline Register Configuration
   ACASCREG => 1,                     -- Number of pipeline stages between A/ACIN and ACOUT (0-2)
   AREG => 1,                         -- Pipeline stages for A (0-2)
   FPA_PREG => 1,                     -- Pipeline stages for FPA output (0-1)
   FPBREG => 1,                       -- Pipeline stages for B inputs (0-1)
   FPCREG => 3,                       -- Pipeline stages for C input (0-3)
   FPDREG => 1,                       -- Pipeline stages for D inputs (0-1)
   FPMPIPEREG => 1,                   -- Selects the number of FPMPIPE registers (0-1)
   FPM_PREG => 1,                     -- Pipeline stages for FPM output (0-1)
   FPOPMREG => 3,                     -- Selects the length of the FPOPMODE pipeline (0-3)
   INMODEREG => 1,                    -- Selects the number of FPINMODE registers (0-1)
   RESET_MODE => "SYNC"               -- Selection of synchronous or asynchronous reset. (ASYNC, SYNC).
)
port map (
   -- Cascade outputs: Cascade Ports
   ACOUT_EXP => ACOUT_EXP,         -- 8-bit output: A exponent cascade data
   ACOUT_MAN => ACOUT_MAN,         -- 23-bit output: A mantissa cascade data
   ACOUT_SIGN => ACOUT_SIGN,       -- 1-bit output: A sign cascade data
   BCOUT_EXP => BCOUT_EXP,         -- 8-bit output: B exponent cascade data
   BCOUT_MAN => BCOUT_MAN,         -- 23-bit output: B mantissa cascade data
   BCOUT_SIGN => BCOUT_SIGN,       -- 1-bit output: B sign cascade data
   PCOUT => PCOUT,                 -- 32-bit output: Cascade output
   -- Data outputs: Data Ports
   FPA_INVALID => FPA_INVALID,     -- 1-bit output: Invalid flag for FPA output
   FPA_OUT => FPA_OUT,             -- 32-bit output: Adder/accumlator data output in Binary32 format.
   FPA_OVERFLOW => FPA_OVERFLOW,   -- 1-bit output: Overflow signal for adder/accumlator data output
   FPA_UNDERFLOW => FPA_UNDERFLOW, -- 1-bit output: Underflow signal for adder/accumlator data output
   FPM_INVALID => FPM_INVALID,     -- 1-bit output: Invalid flag for FPM output
   FPM_OUT => FPM_OUT,             -- 32-bit output: Multiplier data output in Binary32 format.
   FPM_OVERFLOW => FPM_OVERFLOW,   -- 1-bit output: Overflow signal for multiplier data output
   FPM_UNDERFLOW => FPM_UNDERFLOW, -- 1-bit output: Underflow signal for multiplier data output
   -- Cascade inputs: Cascade Ports
   ACIN_EXP => ACIN_EXP,           -- 8-bit input: A exponent cascade data
   ACIN_MAN => ACIN_MAN,           -- 23-bit input: A mantissa cascade data
   ACIN_SIGN => ACIN_SIGN,         -- 1-bit input: A sign cascade data
   BCIN_EXP => BCIN_EXP,           -- 8-bit input: B exponent cascade data
   BCIN_MAN => BCIN_MAN,           -- 23-bit input: B mantissa cascade data
   BCIN_SIGN => BCIN_SIGN,         -- 1-bit input: B sign cascade data
   PCIN => PCIN,                   -- 32-bit input: P cascade
   -- Control inputs: Control Inputs/Status Bits
   CLK => CLK,                     -- 1-bit input: Clock
   FPINMODE => FPINMODE,           -- 1-bit input: Controls select for B/D input data mux.
   FPOPMODE => FPOPMODE,           -- 7-bit input: Selects input signals to floating-point adder and input
                                   -- negation.

   -- Data inputs: Data Ports
   A_EXP => A_EXP,                 -- 8-bit input: A data exponent
   A_MAN => A_MAN,                 -- 23-bit input: A data mantissa
   A_SIGN => A_SIGN,               -- 1-bit input: A data sign bit
   B_EXP => B_EXP,                 -- 8-bit input: B data exponent
   B_MAN => B_MAN,                 -- 23-bit input: B data mantissa
   B_SIGN => B_SIGN,               -- 1-bit input: B data sign bit
   C => C,                         -- 32-bit input: C data input in Binary32 format.
   D_EXP => D_EXP,                 -- 8-bit input: D data exponent
   D_MAN => D_MAN,                 -- 23-bit input: D data mantissa
   D_SIGN => D_SIGN,               -- 1-bit input: D data sign bit
   -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs
   ASYNC_RST => ASYNC_RST,         -- 1-bit input: Asynchronous reset for all registers.
   CEA1 => CEA1,                   -- 1-bit input: Clock enable for 1st stage AREG
   CEA2 => CEA2,                   -- 1-bit input: Clock enable for 2nd stage AREG
   CEB => CEB,                     -- 1-bit input: Clock enable BREG
   CEC => CEC,                     -- 1-bit input: Clock enable for CREG
   CED => CED,                     -- 1-bit input: Clock enable for DREG
   CEFPA => CEFPA,                 -- 1-bit input: Clock enable for FPA_PREG
   CEFPINMODE => CEFPINMODE,       -- 1-bit input: Clock enable for FPINMODE register
   CEFPM => CEFPM,                 -- 1-bit input: Clock enable for FPM output register.
   CEFPMPIPE => CEFPMPIPE,         -- 1-bit input: Clock enable for FPMPIPE post multiplier register.
   CEFPOPMODE => CEFPOPMODE,       -- 1-bit input: Clock enable for FPOPMODE post multiplier register.
   RSTA => RSTA,                   -- 1-bit input: Reset for AREG
   RSTB => RSTB,                   -- 1-bit input: Reset for BREG
   RSTC => RSTC,                   -- 1-bit input: Reset for CREG
   RSTD => RSTD,                   -- 1-bit input: Reset for DREG
   RSTFPA => RSTFPA,               -- 1-bit input: Reset for FPA output register
   RSTFPINMODE => RSTFPINMODE,     -- 1-bit input: Reset for FPINMODE register
   RSTFPM => RSTFPM,               -- 1-bit input: Reset for FPM output register
   RSTFPMPIPE => RSTFPMPIPE,       -- 1-bit input: Reset for FPMPIPE register
   RSTFPOPMODE => RSTFPOPMODE      -- 1-bit input: Reset for FPOPMODE registers
);

-- End of DSPFP32_inst instantiation

Verilog Instantiation Template


// DSPFP32: The DSPFP32 consists of a floating-point multiplier and a floating-point adder  with separate outputs.
//          Versal Prime series
// Xilinx HDL Language Template, version 2021.1

DSPFP32 #(
   // Feature Control Attributes: Data Path Selection
   .A_FPTYPE("B32"),                  // B16, B32
   .A_INPUT("DIRECT"),                // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
   .BCASCSEL("B"),                    // Selects B cascade out data (B, D).
   .B_D_FPTYPE("B32"),                // B16, B32
   .B_INPUT("DIRECT"),                // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
   .PCOUTSEL("FPA"),                  // Select PCOUT output cascade of DSPFP32 (FPA, FPM)
   .USE_MULT("MULTIPLY"),             // Select multiplier usage (DYNAMIC, MULTIPLY, NONE)
   // Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
   .IS_CLK_INVERTED(1'b0),            // Optional inversion for CLK
   .IS_FPINMODE_INVERTED(1'b0),       // Optional inversion for FPINMODE
   .IS_FPOPMODE_INVERTED(7'b0000000), // Optional inversion for FPOPMODE
   .IS_RSTA_INVERTED(1'b0),           // Optional inversion for RSTA
   .IS_RSTB_INVERTED(1'b0),           // Optional inversion for RSTB
   .IS_RSTC_INVERTED(1'b0),           // Optional inversion for RSTC
   .IS_RSTD_INVERTED(1'b0),           // Optional inversion for RSTD
   .IS_RSTFPA_INVERTED(1'b0),         // Optional inversion for RSTFPA
   .IS_RSTFPINMODE_INVERTED(1'b0),    // Optional inversion for RSTFPINMODE
   .IS_RSTFPMPIPE_INVERTED(1'b0),     // Optional inversion for RSTFPMPIPE
   .IS_RSTFPM_INVERTED(1'b0),         // Optional inversion for RSTFPM
   .IS_RSTFPOPMODE_INVERTED(1'b0),    // Optional inversion for RSTFPOPMODE
   // Register Control Attributes: Pipeline Register Configuration
   .ACASCREG(1),                      // Number of pipeline stages between A/ACIN and ACOUT (0-2)
   .AREG(1),                          // Pipeline stages for A (0-2)
   .FPA_PREG(1),                      // Pipeline stages for FPA output (0-1)
   .FPBREG(1),                        // Pipeline stages for B inputs (0-1)
   .FPCREG(3),                        // Pipeline stages for C input (0-3)
   .FPDREG(1),                        // Pipeline stages for D inputs (0-1)
   .FPMPIPEREG(1),                    // Selects the number of FPMPIPE registers (0-1)
   .FPM_PREG(1),                      // Pipeline stages for FPM output (0-1)
   .FPOPMREG(3),                      // Selects the length of the FPOPMODE pipeline (0-3)
   .INMODEREG(1),                     // Selects the number of FPINMODE registers (0-1)
   .RESET_MODE("SYNC")                // Selection of synchronous or asynchronous reset. (ASYNC, SYNC).
)
DSPFP32_inst (
   // Cascade outputs: Cascade Ports
   .ACOUT_EXP(ACOUT_EXP),         // 8-bit output: A exponent cascade data
   .ACOUT_MAN(ACOUT_MAN),         // 23-bit output: A mantissa cascade data
   .ACOUT_SIGN(ACOUT_SIGN),       // 1-bit output: A sign cascade data
   .BCOUT_EXP(BCOUT_EXP),         // 8-bit output: B exponent cascade data
   .BCOUT_MAN(BCOUT_MAN),         // 23-bit output: B mantissa cascade data
   .BCOUT_SIGN(BCOUT_SIGN),       // 1-bit output: B sign cascade data
   .PCOUT(PCOUT),                 // 32-bit output: Cascade output
   // Data outputs: Data Ports
   .FPA_INVALID(FPA_INVALID),     // 1-bit output: Invalid flag for FPA output
   .FPA_OUT(FPA_OUT),             // 32-bit output: Adder/accumlator data output in Binary32 format.
   .FPA_OVERFLOW(FPA_OVERFLOW),   // 1-bit output: Overflow signal for adder/accumlator data output
   .FPA_UNDERFLOW(FPA_UNDERFLOW), // 1-bit output: Underflow signal for adder/accumlator data output
   .FPM_INVALID(FPM_INVALID),     // 1-bit output: Invalid flag for FPM output
   .FPM_OUT(FPM_OUT),             // 32-bit output: Multiplier data output in Binary32 format.
   .FPM_OVERFLOW(FPM_OVERFLOW),   // 1-bit output: Overflow signal for multiplier data output
   .FPM_UNDERFLOW(FPM_UNDERFLOW), // 1-bit output: Underflow signal for multiplier data output
   // Cascade inputs: Cascade Ports
   .ACIN_EXP(ACIN_EXP),           // 8-bit input: A exponent cascade data
   .ACIN_MAN(ACIN_MAN),           // 23-bit input: A mantissa cascade data
   .ACIN_SIGN(ACIN_SIGN),         // 1-bit input: A sign cascade data
   .BCIN_EXP(BCIN_EXP),           // 8-bit input: B exponent cascade data
   .BCIN_MAN(BCIN_MAN),           // 23-bit input: B mantissa cascade data
   .BCIN_SIGN(BCIN_SIGN),         // 1-bit input: B sign cascade data
   .PCIN(PCIN),                   // 32-bit input: P cascade
   // Control inputs: Control Inputs/Status Bits
   .CLK(CLK),                     // 1-bit input: Clock
   .FPINMODE(FPINMODE),           // 1-bit input: Controls select for B/D input data mux.
   .FPOPMODE(FPOPMODE),           // 7-bit input: Selects input signals to floating-point adder and input
                                  // negation.

   // Data inputs: Data Ports
   .A_EXP(A_EXP),                 // 8-bit input: A data exponent
   .A_MAN(A_MAN),                 // 23-bit input: A data mantissa
   .A_SIGN(A_SIGN),               // 1-bit input: A data sign bit
   .B_EXP(B_EXP),                 // 8-bit input: B data exponent
   .B_MAN(B_MAN),                 // 23-bit input: B data mantissa
   .B_SIGN(B_SIGN),               // 1-bit input: B data sign bit
   .C(C),                         // 32-bit input: C data input in Binary32 format.
   .D_EXP(D_EXP),                 // 8-bit input: D data exponent
   .D_MAN(D_MAN),                 // 23-bit input: D data mantissa
   .D_SIGN(D_SIGN),               // 1-bit input: D data sign bit
   // Reset/Clock Enable inputs: Reset/Clock Enable Inputs
   .ASYNC_RST(ASYNC_RST),         // 1-bit input: Asynchronous reset for all registers.
   .CEA1(CEA1),                   // 1-bit input: Clock enable for 1st stage AREG
   .CEA2(CEA2),                   // 1-bit input: Clock enable for 2nd stage AREG
   .CEB(CEB),                     // 1-bit input: Clock enable BREG
   .CEC(CEC),                     // 1-bit input: Clock enable for CREG
   .CED(CED),                     // 1-bit input: Clock enable for DREG
   .CEFPA(CEFPA),                 // 1-bit input: Clock enable for FPA_PREG
   .CEFPINMODE(CEFPINMODE),       // 1-bit input: Clock enable for FPINMODE register
   .CEFPM(CEFPM),                 // 1-bit input: Clock enable for FPM output register.
   .CEFPMPIPE(CEFPMPIPE),         // 1-bit input: Clock enable for FPMPIPE post multiplier register.
   .CEFPOPMODE(CEFPOPMODE),       // 1-bit input: Clock enable for FPOPMODE post multiplier register.
   .RSTA(RSTA),                   // 1-bit input: Reset for AREG
   .RSTB(RSTB),                   // 1-bit input: Reset for BREG
   .RSTC(RSTC),                   // 1-bit input: Reset for CREG
   .RSTD(RSTD),                   // 1-bit input: Reset for DREG
   .RSTFPA(RSTFPA),               // 1-bit input: Reset for FPA output register
   .RSTFPINMODE(RSTFPINMODE),     // 1-bit input: Reset for FPINMODE register
   .RSTFPM(RSTFPM),               // 1-bit input: Reset for FPM output register
   .RSTFPMPIPE(RSTFPMPIPE),       // 1-bit input: Reset for FPMPIPE register
   .RSTFPOPMODE(RSTFPOPMODE)      // 1-bit input: Reset for FPOPMODE registers
);

// End of DSPFP32_inst instantiation

Related Information

Versal ACAP DSP Engine Architecture Manual (AM004)