IBUFDS_INTERMDISABLE - 2021.1 English

Primitive: Differential Input Buffer With Input Buffer Disable and On-die Input Termination Disable

PRIMITIVE_GROUP: I/O
PRIMITIVE_SUBGROUP: INPUT_BUFFER

Introduction

The IBUFDS_INTERMDISABLE primitive is available in the HD I/O banks, is similar to the IBUFDS_IBUFDISABLE primitive because it has a IBUFDISABLE port to disable the input buffer when not in use. The IBUFDS_INTERMDISABLE primitive also has an INTERMDISABLE port to use to disable the optional on-die receiver termination feature.

The IBUFDS_INTERMDISABLE primitive can disable the input buffer and force the O output to a logic-Low when the IBUFDISABLE signal is asserted High. The USE_IBUFDISABLE attribute must be set to TRUE and SIM_DEVICE to to the appropriate value for this primitive to have the expected behavior that is specific to the architecture. If the I/O is using the optional on-die receiver termination feature, this primitive disables the termination legs whenever the INTERMDISABLE signal is asserted High. Both these features can be combined to reduce power whenever the input is idle.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port	Direction	Width	Function
I	Input	1	Diff_p Buffer Input. Connect to top-level p-side input port.
IB	Input	1	Diff_n Buffer Input. Connect to top-level n-side input port.
IBUFDISABLE	Input	1	Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time.
INTERMDISABLE	Input	1	Disables input termination reducing current dissipation within the buffer. This feature is generally used to reduce power at times when the I/O is idle for a period of time.
O	Output	1	Buffer output

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
SIM_DEVICE	STRING	"VERSAL_PRIME", "VERSAL_PRIME_ES1", "VERSAL_PRIME_ES2"	"7SERIES"	Set the device version for simulation functionality.
USE_IBUFDISABLE	STRING	"TRUE", "FALSE"	"TRUE"	Set this attribute to "TRUE" to enable the IBUFDISABLE pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IBUFDS_IBUFDISABLE: Differential Input Buffer With Input Buffer Disable
--                     Versal Prime series
-- Xilinx HDL Language Template, version 2021.1

IBUFDS_IBUFDISABLE_inst : IBUFDS_IBUFDISABLE
generic map (
   SIM_DEVICE => "VERSAL_PRIME", -- Set the device version for simulation functionality (VERSAL_PRIME,
                                 -- VERSAL_PRIME_ES1)
   USE_IBUFDISABLE => "TRUE"     -- Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
port map (
   O => O,                     -- 1-bit output: Buffer output
   I => I,                     -- 1-bit input: Diff_p buffer input (connect directly to top-level port)
   IB => IB,                   -- 1-bit input: Diff_n buffer input (connect directly to top-level port)
   IBUFDISABLE => IBUFDISABLE  -- 1-bit input: Buffer input disable, high=disable
);

-- End of IBUFDS_IBUFDISABLE_inst instantiation

Verilog Instantiation Template


// IBUFDS_IBUFDISABLE: Differential Input Buffer With Input Buffer Disable
//                     Versal Prime series
// Xilinx HDL Language Template, version 2021.1

IBUFDS_IBUFDISABLE #(
   .SIM_DEVICE("VERSAL_PRIME"), // Set the device version for simulation functionality (VERSAL_PRIME,
                                // VERSAL_PRIME_ES1)
   .USE_IBUFDISABLE("TRUE")     // Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
IBUFDS_IBUFDISABLE_inst (
   .O(O),                     // 1-bit output: Buffer output
   .I(I),                     // 1-bit input: Diff_p buffer input (connect directly to top-level port)
   .IB(IB),                   // 1-bit input: Diff_n buffer input (connect directly to top-level port)
   .IBUFDISABLE(IBUFDISABLE)  // 1-bit input: Buffer input disable, high=disable
);

// End of IBUFDS_IBUFDISABLE_inst instantiation

Related Information

Versal ACAP SelectIO Resources Architecture Manual (AM010)