MBUFG_GT - 2021.1 English

Primitive: Multi-Output Clock Buffer Driven by Gigabit Transceiver

PRIMITIVE_GROUP: CLOCK
PRIMITIVE_SUBGROUP: BUFFER

Introduction

Multi-Output clock buffer driven by the gigabit transceiver for the purpose of clock distribution to other portions of the device.

Port Descriptions

Port	Direction	Width	Function
CE	Input	1	Buffer enable
CEMASK	Input	1	CE Mask
CLR	Input	1	Asynchronous clear forcing the output to zero.
CLRB_LEAF	Input	1	Active low clear of BUFDIV_LEAF
CLRMASK	Input	1	CLR Mask
DIV<2:0>	Input	3	Specifies the value to divide the clock. Divide value is value provided plus 1. For instance, setting 3'b000 will provide a divide value of 1 and 3'b111 will be a divide value of 8.
I	Input	1	Buffer Input
O1	Output	1	I in PERFORMANCE MODE I*2 in POWER MODE Note: Connecting the DIV<2:0> pins to a non-zero value will result in futher division of the output clock by that factor.
O2	Output	1	I/2 in PERFORMANCE MODE I in POWER MODE Note: Connecting the DIV<2:0> pins to a non-zero value will result in futher division of the output clock by that factor.
O3	Output	1	I/4 in PERFORMANCE MODE I/2 in POWER MODE Note: Connecting the DIV<2:0> pins to a non-zero value will result in futher division of the output clock by that factor.
O4	Output	1	I/8 in PERFORMANCE MODE I/4 in POWER MODE Note: Connecting the DIV<2:0> pins to a non-zero value will result in futher division of the output clock by that factor.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	Recommended

Available Attributes

Attribute	Type	Allowed Values	Default	Description
MODE	STRING	"PERFORMANCE", "POWER"	"PERFORMANCE"	Sets the mode of operation that determines the output clock generation. For PERFORMANCE MODE, the outputs are generated as follows: O1 = I O2 = I/2 O3 = I/4 O4 = I/8 For POWER MODE, the outputs are generated as follows: O1 = I*2 O2 = I O3 = I/2 O4 = I/4 Note: Connecting the DIV<2:0> pins to a non-zero value will result in futher division of the output clock by that factor.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- MBUFG_GT: Multi-Output Clock Buffer Driven by Gigabit Transceiver
--           Versal Prime series
-- Xilinx HDL Language Template, version 2021.1

MBUFG_GT_inst : MBUFG_GT
generic map (
   MODE => "PERFORMANCE"  -- PERFORMANCE, POWER
)
port map (
   O1 => O1,               -- 1-bit output: Buffer
   O2 => O2,               -- 1-bit output: Buffer
   O3 => O3,               -- 1-bit output: Buffer
   O4 => O4,               -- 1-bit output: Buffer
   CE => CE,               -- 1-bit input: Buffer enable
   CEMASK => CEMASK,       -- 1-bit input: CE Mask
   CLR => CLR,             -- 1-bit input: Asynchronous clear
   CLRB_LEAF => CLRB_LEAF, -- 1-bit input: Active low clear
   CLRMASK => CLRMASK,     -- 1-bit input: CLR Mask
   DIV => DIV,             -- 3-bit input: Dynamic divide Value
   I => I                  -- 1-bit input: Buffer
);

-- End of MBUFG_GT_inst instantiation

Verilog Instantiation Template


// MBUFG_GT: Multi-Output Clock Buffer Driven by Gigabit Transceiver
//           Versal Prime series
// Xilinx HDL Language Template, version 2021.1

MBUFG_GT #(
   .MODE("PERFORMANCE")  // PERFORMANCE, POWER
)
MBUFG_GT_inst (
   .O1(O1),               // 1-bit output: Buffer
   .O2(O2),               // 1-bit output: Buffer
   .O3(O3),               // 1-bit output: Buffer
   .O4(O4),               // 1-bit output: Buffer
   .CE(CE),               // 1-bit input: Buffer enable
   .CEMASK(CEMASK),       // 1-bit input: CE Mask
   .CLR(CLR),             // 1-bit input: Asynchronous clear
   .CLRB_LEAF(CLRB_LEAF), // 1-bit input: Active low clear
   .CLRMASK(CLRMASK),     // 1-bit input: CLR Mask
   .DIV(DIV),             // 3-bit input: Dynamic divide Value
   .I(I)                  // 1-bit input: Buffer
);

// End of MBUFG_GT_inst instantiation

Related Information

Versal ACAP Clocking Resources Architecture Manual (AM003)