RAM32X16DR8 - 2021.1 English

Versal Architecture Prime Series Libraries Guide (UG1344)
Document ID
UG1344
Release Date
2021-06-16
Version
2021.1 English

Primitive: Asymmetric LUTRAM

  • PRIMITIVE_GROUP: CLB
  • PRIMITIVE_SUBGROUP: LUTRAM

Introduction

This design element is a 32-Deep Asymmetric LUTRAM. The write size (32*14) is twice the read size (64*7) and fits into a single slice.

Port Descriptions

Port Direction Width Function
ADDRA<5:0> Input 6 Read port A address input.
ADDRB<5:0> Input 6 Read port B address input.
ADDRC<5:0> Input 6 Read port C address input.
ADDRD<5:0> Input 6 Read port D address input.
ADDRE<5:0> Input 6 Read port E address input.
ADDRF<5:0> Input 6 Read port F address input.
ADDRG<5:0> Input 6 Read port G address input.
ADDRH<4:0> Input 5 Read/write port H address input.
DIA<1:0> Input 2 RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRA.
DIB<1:0> Input 2 RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRB.
DIC<1:0> Input 2 RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRC.
DID<1:0> Input 2 RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRD.
DIE<1:0> Input 2 RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRE.
DIF<1:0> Input 2 RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRF.
DIG<1:0> Input 2 RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRG.
DIH<1:0> Input 2 RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRH.
DOA Output 1 Read port data outputs addressed by ADDRA.
DOB Output 1 Read port data outputs addressed by ADDRB.
DOC Output 1 Read port data outputs addressed by ADDRC.
DOD Output 1 Read port data outputs addressed by ADDRD.
DOE Output 1 Read port data outputs addressed by ADDRE.
DOF Output 1 Read port data outputs addressed by ADDRF.
DOG Output 1 Read port data outputs addressed by ADDRG.
DOH<1:0> Output 2 Read port data outputs addressed by ADDRH.
WCLK Input 1 Write clock.
WE Input 1 Write Enable.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
IS_WCLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the WCLK pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- RAM32X16DR8: Asymmetric LUTRAM
--              Versal Prime series
-- Xilinx HDL Language Template, version 2021.1

RAM32X16DR8_inst : RAM32X16DR8
generic map (
   IS_WCLK_INVERTED => '0'  -- Specifies active high/low WCLK
)
port map (
   DOA => DOA,     -- 1-bit output: Read port A 1-bit output
   DOB => DOB,     -- 1-bit output: Read port B 1-bit output
   DOC => DOC,     -- 1-bit output: Read port C 1-bit output
   DOD => DOD,     -- 1-bit output: Read port D 1-bit output
   DOE => DOE,     -- 1-bit output: Read port E 1-bit output
   DOF => DOF,     -- 1-bit output: Read port F 1-bit output
   DOG => DOG,     -- 1-bit output: Read port G 1-bit output
   DOH => DOH,     -- 2-bit output: Read port H 1-bit output
   ADDRA => ADDRA, -- 6-bit input: Read port A 6-bit address input
   ADDRB => ADDRB, -- 6-bit input: Read port B 6-bit address input
   ADDRC => ADDRC, -- 6-bit input: Read port C 6-bit address input
   ADDRD => ADDRD, -- 6-bit input: Read port D 6-bit address input
   ADDRE => ADDRE, -- 6-bit input: Read port E 6-bit address input
   ADDRF => ADDRF, -- 6-bit input: Read port F 6-bit address input
   ADDRG => ADDRG, -- 6-bit input: Read port G 6-bit address input
   ADDRH => ADDRH, -- 5-bit input: Read/write port H 5-bit address input
   DIA => DIA,     -- 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRA.
   DIB => DIB,     -- 2-bit input: RAM 2-bit data write input addressed by ADDRH,  read addressed by ADDRB.
   DIC => DIC,     -- 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRC.
   DID => DID,     -- 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRD.
   DIE => DIE,     -- 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRE.
   DIF => DIF,     -- 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRF.
   DIG => DIG,     -- 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRG.
   DIH => DIH,     -- 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRH.
   WCLK => WCLK,   -- 1-bit input: Write clock input
   WE => WE        -- 1-bit input: Write enable input
);

-- End of RAM32X16DR8_inst instantiation

Verilog Instantiation Template


// RAM32X16DR8: Asymmetric LUTRAM
//              Versal Prime series
// Xilinx HDL Language Template, version 2021.1

RAM32X16DR8 #(
   .IS_WCLK_INVERTED(1'b0)  // Specifies active high/low WCLK
)
RAM32X16DR8_inst (
   .DOA(DOA),     // 1-bit output: Read port A 1-bit output
   .DOB(DOB),     // 1-bit output: Read port B 1-bit output
   .DOC(DOC),     // 1-bit output: Read port C 1-bit output
   .DOD(DOD),     // 1-bit output: Read port D 1-bit output
   .DOE(DOE),     // 1-bit output: Read port E 1-bit output
   .DOF(DOF),     // 1-bit output: Read port F 1-bit output
   .DOG(DOG),     // 1-bit output: Read port G 1-bit output
   .DOH(DOH),     // 2-bit output: Read port H 1-bit output
   .ADDRA(ADDRA), // 6-bit input: Read port A 6-bit address input
   .ADDRB(ADDRB), // 6-bit input: Read port B 6-bit address input
   .ADDRC(ADDRC), // 6-bit input: Read port C 6-bit address input
   .ADDRD(ADDRD), // 6-bit input: Read port D 6-bit address input
   .ADDRE(ADDRE), // 6-bit input: Read port E 6-bit address input
   .ADDRF(ADDRF), // 6-bit input: Read port F 6-bit address input
   .ADDRG(ADDRG), // 6-bit input: Read port G 6-bit address input
   .ADDRH(ADDRH), // 5-bit input: Read/write port H 5-bit address input
   .DIA(DIA),     // 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRA.
   .DIB(DIB),     // 2-bit input: RAM 2-bit data write input addressed by ADDRH,  read addressed by ADDRB.
   .DIC(DIC),     // 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRC.
   .DID(DID),     // 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRD.
   .DIE(DIE),     // 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRE.
   .DIF(DIF),     // 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRF.
   .DIG(DIG),     // 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRG.
   .DIH(DIH),     // 2-bit input: RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRH.
   .WCLK(WCLK),   // 1-bit input: Write clock input
   .WE(WE)        // 1-bit input: Write enable input
);

// End of RAM32X16DR8_inst instantiation

Related Information

  • Versal ACAP Configurable Logic Block Architecture Manual (AM005)