OR2L - 2021.1 English

Primitive: Two input OR gate implemented in place of a CLB Latch

PRIMITIVE_GROUP: CLB
PRIMITIVE_SUBGROUP: LATCH

Introduction

This element allows the specification of a configurable CLB latch to take the function of a two input OR gate. The use of this element can reduce logic levels and increase logic density of the part by trading off register/latch resources for logic. Xilinx suggests caution when using this component as it can affect register packing and density within a CLB.

Logic Table

Inputs		Outputs
DI	SRI	O
0	0	0
0	1	1
1	0	1
1	1	1

Port Descriptions

Port	Direction	Width	Function
DI	Input	1	Active-High input that is generally connected to sourcing LUT located in the same CLB.
O	Output	1	Output of the OR gate.
SRI	Input	1	Input that is generally sourced from outside of the CLB. The attribute IS_SRI_INVERTED determines the active polarity of this signal. Note: To allow more than one AND2B1L or OR2L to be packed into a half CLB, a common signal must be connected to this input.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
IS_SRI_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion for the SRI pin of this component.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- OR2L: Two input OR gate implemented in place of a CLB Latch
--       Versal Prime series
-- Xilinx HDL Language Template, version 2021.1

OR2L_inst : OR2L
generic map (
   IS_SRI_INVERTED => '0'  -- Optional inversion for SRI
)
port map (
   O => O,     -- 1-bit output: OR gate output
   DI => DI,   -- 1-bit input: Data input connected to LUT logic
   SRI => SRI  -- 1-bit input: External CLB data
);

-- End of OR2L_inst instantiation

Verilog Instantiation Template


// OR2L: Two input OR gate implemented in place of a CLB Latch
//       Versal Prime series
// Xilinx HDL Language Template, version 2021.1

OR2L #(
   .IS_SRI_INVERTED(1'b0)  // Optional inversion for SRI
)
OR2L_inst (
   .O(O),     // 1-bit output: OR gate output
   .DI(DI),   // 1-bit input: Data input connected to LUT logic
   .SRI(SRI)  // 1-bit input: External CLB data
);

// End of OR2L_inst instantiation

Related Information

Versal ACAP Configurable Logic Block Architecture Manual (AM005)