Versal ACAP Power Domains - 2020.2 English

Versal ACAP System Software Developers Guide (UG1304)

Document ID
Release Date
2020.2 English

The Versal device is divided into following power domains:

Full power domain (FPD)
Contains the ArmĀ® Cortex-A72 application processor unit (APU).
Low power domain (LPD)
Contains the Arm Cortex-R5F real-time processor unit (RPU), and on-chip peripherals.
System power domain (SPD)
Contains the DDR controllers and NoC.
PL power domain
Contains the PL and the AI Engine.
Battery power domain
Contains the real-time clock (RTC) as well as battery-backed RAM (BBRAM).
PMC power domain
Contains the platform management controller.

The battery and PMC power domains are not managed by the framework. Designs that want to take advantage of the platform management switching the power domains, must keep some power rails discrete. This allows individual rails to be powered off with the power domain switching logic.

The following figure illustrates the Versal device power domains and islands.

Figure 1. Power Domains and Islands Diagram

Because of the heterogeneous multi-core architecture of the Versal ACAP, no processor can make autonomous decisions about power states of individual components or subsystems.

Instead, a collaborative approach is taken, where a power management API delegates all power management control to the platform management controller (PMC). The PMC is the key component in coordinating the power management requests received from the other processing units, such as the APU or the RPU, and the coordination and execution from other processing units through the power management API.

Versal ACAP also supports inter-processor interrupts (IPIs), which are used as the basis for platform management related communication between the different processors. For more information, refer to the interrupts information in the Versal ACAP Technical Reference Manual (AM011).