AI Engine Development Environment - 2020.2 English

Versal ACAP System Software Developers Guide (UG1304)

Document ID
UG1304
Release Date
2020-11-24
Version
2020.2 English

The Versal AI Core series delivers breakthrough AI inference acceleration with AI Engines that deliver over 100x greater compute performance than current server-class of CPUs. This series is designed for a breadth of applications, including cloud for dynamic workloads and network for massive bandwidth, all while delivering advanced safety and security features. AI and data scientists, as well as software and hardware developers, can all take advantage of the high compute density to accelerate the performance of any application. Given the AI Engine's advanced signal processing compute capability, it is well-suited for highly optimized wireless applications such as radio, 5G, backhaul, and other high-performance DSP applications.

AI Engines are an array of very-long instruction word (VLIW) processors with single instruction multiple data (SIMD) vector units that are highly optimized for compute-intensive applications, specifically digital signal processing (DSP), 5G wireless applications, and artificial intelligence (AI) technology such as machine learning (ML).

AI Engines provide multiple levels of parallelism including instruction-level and data-level parallelism. Instruction-level parallelism includes a scalar operation, up to two moves, two vector reads (loads), one vector write (store), and one vector instruction that can be executed—in total, a 7-way VLIW instruction per clock cycle. Data-level parallelism is achieved via vector-level operations where multiple sets of data can be operated on a per-clock-cycle basis. Each AI Engine contains both a vector and scalar processor, dedicated program memory, local 32 KB data memory, access to local memory in any of three neighboring directions. It also has access to DMA engines and AXI4 interconnect switches to communicate via streams to other AI Engines or to the programmable logic (PL) or the DMA. Refer to the Versal ACAP AI Engine Architecture Manual (AM009) for specific details on the AI Engine array and interfaces.

Xilinx® provides device drivers and libraries for user applications to access the Versal™ AI Engines. See Versal ACAP AI Engine Programming Environment User Guide (UG1076) (Registration required) to learn how to use the Xilinx® AI Engine program environment. The Vitis IDE lets you compile, simulate, and debug the different elements of a Versal ACAP AI Engine application. For detailed information on the Vitis IDE tool flow, refer to Versal ACAP Design Guide (UG1273). For detailed information on the Vitis AL Engine Tools and Flows, refer to Versal ACAP AI Engine Programming Environment User Guide (UG1076) (Registration required).

The following sections describe the software stack of the AI Engine.