Hardware Overview - 2020.2 English

Versal ACAP System Software Developers Guide (UG1304)

Document ID
Release Date
2020.2 English

This section provides an overview of the Versal ACAP hardware view components.

Note: For more detailed information about the Versal ACAP hardware, refer to the Versal ACAP Technical Reference Manual (AM011).
Figure 1. System-level Interconnect Architecture

Key Hardware Components

The following list describes the largest hardware view components:

AI Engine
The AI Engine is used for custom acceleration and compute engines.
The application processing unit (APU) consists of Cortex-A72 processor cores, L1/L2 caches, and related functionality. The Cortex-A72 cores and caches are part of Arm MPCore IP.

Versal ACAP uses a dual-core Cortex-A72 processor system with 1 MB L2 cache. The Cortex-A72 cores implement Armv8 64-bit architecture. The Cortex-A72 MPCore does not have integrated generic interrupt controller (GIC), so an external GIC IP is used. For more information, refer to "APU Processor Features" in Versal ACAP Technical Reference Manual (AM011).

AXI Interconnect
The Advanced eXtensible Interface interconnect connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specifications from Arm, including the AXI4-Lite control register interface subset.
The interconnect for Cache Coherent Interconnect for Accelerators (CCIX) and PCIe® (CPM) module is the primary PCIe interface for the processing system. There are two integrated blocks for PCIe in the CPM, supporting up to Gen4 x16. You can configure both of the integrated blocks for PCIe as an endpoint. Furthermore, you can configure each integrated block as a root port that contains direct memory access (DMA) logic. The CPM also incorporates CCIX functionality to allow a PL accelerator to act as a CCIX compliant accelerator.
The programmable logic (PL) is a scalable structure that includes adaptable engines and intelligent engines that can be used to construct accelerators, processors, or almost any other complex functionality. It is configured using the Vivado® tools. The architect determines the components to be available in the PL design. For example, the MicroBlaze processor is just an IP core, so you can optionally add MicroBlaze processors to the design. For more info, refer to "Programmable Logic" in Versal ACAP Technical Reference Manual (AM011).
The platform management controller (PMC) handles device management control functions such as device reset sequencing, initialization, boot, configuration, security, power management, dynamic function eXchange (DFX), health-monitoring, and error management. You can boot the device in either secure or non-secure mode. For more information, refer to "Platform Management Controller" in Versal ACAP Technical Reference Manual (AM011).
NoC Interconnect
The NoC is the main interconnect and contains a vertical component (VNoC) and a horizontal component (HNoC).
  • HNoC is integrated in the horizontal super row/region (HSR). The HSR includes blocks such as XPIO, hard DDR memory controller, PLL, System Monitor satellites, HBM, and ME.
  • VNoC integration includes global-clk-column, and System Monitor satellites. In SSI technology, VNoCs are connected across super logic region (SLR) boundaries. Microbumps and buffers for this reside in the Thin-HNoC. Configuration data between SSI technology master and slaves travels over the NoC.
The real-time processing unit (RPU) is a dual-core Cortex-R5F processor, based on the Armv7-R architecture, which can run as either two independent cores or in a lock-step configuration. For more information, refer to "Platform Management" in Versal ACAP Technical Reference Manual (AM011).

Additional Hardware Components

Peripheral Controllers
The input/output units (IOPs) present in the PS module contains the low speed peripherals in low power domain (LPD) and high-speed peripherals in full power domain (FPD). Some IOPs are present in the PMC power domain (PPD) peripherals.

For more information, refer to "I/O Peripherals" in Versal ACAP Technical Reference Manual (AM011).

Interconnects and Buses
Versal ACAP has following additional interconnects and buses:
The NoC programming interface, a 32-bit programming interface to the NoC and several attached units.

For more information, refer to Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).

The advanced peripheral (APB) bus is a 32-bit single-word read/write bus interface. This bus is used to access control registers in the functional units, i.e., subsystem units. These control registers are used to program the functional units. The APB switch is used as the main switch in the following four areas:
  • PMC
  • LPD
  • FPD
  • CPM
The configuration frame interface (CFI) transports the configuration information contained in the boot image from the PMC to its destination within the Versal device. CFI provides a dedicated high-bandwidth 128-bit bus to PL for configuration and readback. For more information, refer "CFI" in Versal ACAP Technical Reference Manual (AM011).
System Watchdog Timer
The system watchdog (SWDT) timer is used to detect and recover from various malfunctions. The watchdog timer can be used to prevent system lockup (when the software becomes trapped in a deadlock). For more information, refer to "System Watchdog Timer" in Versal ACAP Technical Reference Manual (AM011).
Versal ACAP has the following clocks:
  • PMC and PS clocks
  • CPM clocks
  • NoC, AI Engine, and DDR memory controller clocks
  • PL clocks

For more information, refer to the "Clocks" chapter in Versal ACAP Technical Reference Manual (AM011).

Versal device has following list of memories:
DDR Memory
Up to 12 GB of RAM is supported. This DDR memory is external to the device.
On-chip memory (OCM) in the PS
This memory is 256 KB in size, and is also accessible by the RPU.
Tightly coupled memory (TCM) in the RPU
This memory is 256 KB and is mainly used by the RPU but can be accessed by the APU.
Battery-backed RAM (BBRAM)
This memory stores the advanced encryption standard (AES) 256-bit key.
Accelerator RAM (XRAM)
4 MB memory size present in some Versal devices.
2,048-bits of user memory, stores multiple keys, and stores security configuration settings
Versal ACAP has several layers of resets with overlapping effects. The highest-level resets are generally aligned with power domains, then power island resets, and finally the individual functional unit resets. In some cases, functional units have local resets that affects part of the block. The reset hierarchy:
  • Subsystem resets (power domains)
  • Power-island resets
  • Functional unit (block) resets
  • Partial resets of a block (some cases)

For more information, refer to "Memory Virtualization" in Versal ACAP Technical Reference Manual (AM011).

The Versal device includes the following three hardware components for virtualization:
  • CPU virtualization
  • Memory virtualization
  • Interrupt virtualization

For more information, refer to "Memory Virtualization" in Versal ACAP Technical Reference Manual (AM011).

Security and Safety
The Versal device has the following security management and safety features:
  • Secure key storage and management
  • Tamper monitoring and response
  • User access to Xilinx hardware cryptographic accelerators
  • Xilinx memory protection unit (XMPU) and Xilinx peripheral protection unit (XPPU) provides hardware-enforced isolation.
  • TrustZone

For more information, refer to "Platform Management Controller" in Versal ACAP Technical Reference Manual (AM011) and also Security. For XMPU and XPPU, refer to "Memory Protection" in Versal ACAP Technical Reference Manual (AM011).