Processing System - 2020.2 English

Versal ACAP System Software Developers Guide (UG1304)

Document ID
Release Date
2020.2 English

The processing system (PS) has the following components:

  • Dual-core Arm Cortex-A72 processor with 1 MB L2 cache with error correction code (ECC)
  • Dual 32-bit Cortex-R5F processor cores based on the Arm® v7-R architecture and supports both RPU with 128 KB TCM with error correction code (ECC) and Single Lockstep R5 with 128 KB TCM with ECC.
  • 256 KB on-chip memory with error correction code (ECC)
  • Arm CoreSight™ debug and trace (DAP) with TMC, STM, ATM, and APM
  • System memory management unit (SMMU)
  • CCI
  • One universal serial bus (USB) 2.0
  • PCIe RP/EP in CPM (device dependent)
  • Two gigabit Ethernet MAC with TSN support
  • One low-power domain DMA (LPD-DMA)
  • Performance I/O
  • Two controller area network-flexible data rates (CAN-FD), two serial peripheral interfaces (SPI), two I2C, and two UART controllers
  • PS management controller (PSM)
Note: The PS has access to shared external DDR.