BootROM, PLM Handoff State
The BootROM loads the PLM into the PPU RAM from the boot device and is responsible for releasing the PPU from reset to start the PLM execution..
The PLM ELF is loaded to the PPU RAM. The PMC RAM is used to load the PMC DATA CDO file.
The state of the system at BootROM handoff is as follows:
- The PPU is sleeping with the reset released, in case of normal JTAG boot mode.
- The PPU RAM and PMC RAM are initialized with error code correction (ECC).
- The JTAG IDCODE instruction is always available regardless of the boot mode. Except the JTAG IDCODE instruction, all other JTAG instructions can be disabled when you program the required eFUSEs. If the eFUSEs are not programmed and a secure boot occurs, then only the base JTAG instructions are supported. When the AUTH_JTAG enable instruction is sent to the Versal ACAP in a secure boot mode, the full set of JTAG instructions (base +extended) can be enabled.
- The boot device is taken out of reset and initialized.
- The NoC default configuration is enabled for Slave Super Logic Region (SLRs), so that the master PLM can connect to slave PMC devices.
PLM Subsystem
File | Contents |
---|---|
PLM ELF | PLM ELF File |
PMC CDO | PMC CDO file
|
The BootROM loads the PLM ELF and PMC CDO files to the PPU RAM and PMC RAM, respectively.
After the BootROM handoff to the PLM:
- Initialize the PPU and register interrupts.
- Initialize the modules to register the CDO/IPI commands and handlers.
- Configure the PMC CDO file.
- Device topology with PMC CDO commands to registers the nodes.
- General/platform management calls to initialize the PMC
and LPD MIO, clocks, etc.
- PMC initialization for clocks, MIOs, resets.
LPD Configuration
File | Contents |
---|---|
LPD CDO |
|
PSM ELF | PSM ELF file |
After initializing the PMC CDO:
- The PLM initializes the boot device and loads the LPD CDO file from the boot device.
-
- Configures the LPD CDO file.
- Initiates the Scan Clear, BISRs, MBIST as required for LPD.
- XilPM releases resets and powers up the nodes based on the CDO requirements.
- The PLM loads the PSM ELF file and waits until initialization is complete.
Before loading the LPD configuration, ensure that PMC is configured.
PL Configuration
File | Contents |
---|---|
PL CDO <.rcdo> |
|
NPI CDO <.rnpi> | NPI data
|
The NPI data is generated by the Vivado tool for the various NPI blocks. The NPI blocks that are present in Versal ACAP include NoC, DDR, XPHY, XPIO, GTY, MMCMs, etc.
Before loading the PL configuration, ensure that PMC is configured.
FPD Configuration
File | Contents |
---|---|
FPD CDO |
|
Before loading the FPD CDO, ensure that the PMC and LPD are configured.
DFX Configuration
Dynamic Function eXchange (DFX) configuration enables one or more sub-regions of the device to be independently reprogrammed with new configuration data while all remaining regions (static or reconfigurable) remain active and unaffected. The DFX PDI can come either from PCIe, DDR, or the primary boot device. For loading the DFX PDIs, the XilLoader CDO commands are with the IPI interface.
CPM Configuration
- CPM: CPM configuration CDO with register writes
Before loading the CPM CDO, ensure that the PMC, LPD and stage1 PL configuration are completed. Stage1 PL configuration should contain XPIPE, GT, and NoC configuration data in the NPI file.
Processor Subsystem Configuration
The APU and RPU come under the processor- based subsystems. For all processor-based subsystems, ELF files and/or CDOs are present as a part of the image. Processor details are read from image headers and the processor is initialized using XilPM commands.
The configuration consists of the following files.
File | Contents |
---|---|
PSM/RPU/APU CDO files |
|
PSM/RPU/APU ELF files |
|
- For loading Cortex-R5F processor applications, ensure that the LPD configuration is completed.
- For loading Cortex-A72 processor applications, ensure that the FPD configuration is completed.
- For loading Cortex-R5F/Cortex-A72 using DDR memory, ensure that the PL (NPI with DDR configuration) configuration is completed.
- For loading Cortex-R5F/Cortex-A72 processor applications to the DDR, enable the NoC path from the PMC to the DDR in the design.
AI Engine Configuration
The AI Engine configuration consists of the following files.
File | Contents |
---|---|
AI Engine NPI CDO |
AI Engine
Global Configuration using NPI
|
AI Engine ELF | AI Engine tile program and data memory |
AI Engine CDO |
AI Engine
array configuration
|
Before loading the AI Engine NPI CDO, ensure that PLM, LPD and PL (with NoC configuration in the NPI file) are completed. Also, enable the NoC path from the PMC to the AI Engine in the design for PLM to clear the AI Engine data memories.