To minimize consumption of routing resources, the various clock and data signals take on different functions depending on the configured MRMAC operating mode. The following table details the meaning of the various clock and data signals for the given MRMAC configuration settings. For FEC only modes, data/clocks are shared with the transceiver interface.
MRMAC Configuration | Active MRMAC Port | Number of Active GT Lanes | Active GT Clocks | Active GT Interface Data Bus |
---|---|---|---|---|
10/25GE Narrow SerDes |
0 | 1 | rx_serdes_clk[0] | rx_serdes_data0[39:0] |
tx_core_clk[0] | tx_serdes_data0[39:0] | |||
1 | 1 | rx_serdes_clk[1] | rx_serdes_data1[39:0] | |
tx_core_clk[1] | tx_serdes_data1[39:0] | |||
2 | 1 | rx_serdes_clk[2] | rx_serdes_data2[39:0] | |
tx_core_clk[2] | tx_serdes_data2[39:0] | |||
3 | 1 | rx_serdes_clk[3] | rx_serdes_data3[39:0] | |
tx_core_clk[3] | tx_serdes_data3[39:0] | |||
10/25GE Wide SerDes |
0 | 1 | rx_serdes_clk[0] rx_alt_serdes_clk[0] |
rx_serdes_data0[79:0] fec_rx_din_start_0 |
tx_core_clk[0] tx_alt_serdes_clk[0] |
tx_serdes_data0[79:0] fec_tx_dout_start_0 |
|||
1 | 1 | rx_serdes_clk[1] rx_alt_serdes_clk[1] |
rx_serdes_data1[79:0] fec_rx_din_start_1 |
|
tx_core_clk[1] tx_alt_serdes_clk[1] |
tx_serdes_data1[79:0] fec_tx_dout_start_1 |
|||
2 | 1 | rx_serdes_clk[2] rx_alt_serdes_clk[2] |
rx_serdes_data2[79:0] fec_rx_din_start_2 |
|
tx_core_clk[2] tx_alt_serdes_clk[2] |
tx_serdes_data2[79:0] fec_tx_dout_start_2 |
|||
3 | 1 | rx_serdes_clk[3] rx_alt_serdes_clk[3] |
rx_serdes_data3[79:0] fec_rx_din_start_3 |
|
tx_core_clk[3] tx_alt_serdes_clk[3] |
tx_serdes_data3[79:0] fec_tx_dout_start_3 |
|||
40GE Narrow SerDes |
0 | 4 | rx_serdes_clk[0]
rx_serdes_clk[1] rx_serdes_clk[2] rx_serdes_clk[3] |
rx_serdes_data0[15:0] rx_serdes_data1[15:0] rx_serdes_data2[15:0] rx_serdes_data3[15:0] |
tx_core_clk[0] | tx_serdes_data0[15:0] tx_serdes_data1[15:0] tx_serdes_data2[15:0] tx_serdes_data3[15:0] |
|||
40GE Wide SerDes |
0 | 4 | rx_serdes_clk[0] rx_serdes_clk[1] rx_serdes_clk[2] rx_serdes_clk[3] rx_alt_serdes_clk[0] rx_alt_serdes_clk[1] rx_alt_serdes_clk[2] rx_alt_serdes_clk[3] |
rx_serdes_data0[32:0] rx_serdes_data1[32:0] rx_serdes_data2[32:0] rx_serdes_data3[32:0] |
tx_core_clk[0] tx_alt_serdes_clk[0] tx_alt_serdes_clk[1] tx_alt_serdes_clk[2] |
tx_serdes_data0[32:0] tx_serdes_data1[32:0] tx_serdes_data2[32:0] tx_serdes_data3[32:0] |
|||
50GE Narrow SerDes |
0 | 1 | rx_serdes_clk[0] | rx_serdes_data0[39:0] |
tx_core_clk[0] | tx_serdes_data0[39:0] | |||
2 | rx_serdes_clk[1] | rx_serdes_data1[39:0] | ||
N/A | tx_serdes_data1[39:0] | |||
2 | 1 | rx_serdes_clk[2] | rx_serdes_data2[39:0] | |
tx_core_clk[2] | tx_serdes_data2[39:0] | |||
2 | rx_serdes_clk[3] | rx_serdes_data3[39:0] | ||
N/A | tx_serdes_data3[39:0] | |||
50GE Wide SerDes |
0 | 2 | rx_serdes_clk[0] rx_alt_serdes_clk[0] |
rx_serdes_data0[79:0] fec_rx_din_start_0 |
tx_core_clk[0] tx_alt_serdes_clk[0] |
tx_serdes_data0[79:0] fec_tx_dout_start_0 |
|||
2 | 2 | rx_serdes_clk[2] rx_alt_serdes_clk[2] |
rx_serdes_data2[79:0] fec_rx_din_start_2 |
|
tx_core_clk[2] tx_alt_serdes_clk[2] |
tx_serdes_data2[79:0] fec_tx_dout_start_2 |
|||
100GE Narrow SerDes |
0 | 4 | rx_serdes_clk[0] rx_serdes_clk[1] rx_serdes_clk[2] rx_serdes_clk[3] |
rx_serdes_data0[39:0] rx_serdes_data1[39:0] rx_serdes_data2[39:0] rx_serdes_data3[39:0] |
tx_core_clk[0] | tx_serdes_data0[39:0] tx_serdes_data1[39:0] tx_serdes_data2[39:0] tx_serdes_data3[39:0] |
|||
100GE Wide SerDes |
0 | 4 | rx_serdes_clk[0]
rx_serdes_clk[1] rx_serdes_clk[2] rx_serdes_clk[3] |
rx_serdes_data0[79:0] rx_serdes_data1[79:0] rx_serdes_data2[79:0] rx_serdes_data3[79:0] |
tx_core_clk[0] tx_alt_serdes_clk[0] |
tx_serdes_data0[79:0] tx_serdes_data1[79:0] tx_serdes_data2[79:0] tx_serdes_data3[79:0] |
|||
|
The design must satisfy several rules when connecting the MRMAC to the transceivers. See the Transceiver Selection Rules section for details.