S/W driver Core initialization - 1.5 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

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1.5 English

Its recommended that the S/W drivers follow these steps sequentially to properly initialize the core.

  1. Initialize other elements of the design such that the clocks (including ts_clk, and any tx/rx_phy_clk* clocks) are present and stable. Release the resets for those clock domains (ie. ts_rst, tx/rx_phy_rst*).
  2. Configure the TOD_CONFIG register:
    • In Timer or Timer Syncer mode set bit [0] to enable the System Timer.
    • If an external ToD bus (1PPS synchronization and optionally serial seconds input) is to be used, then set bit [1] to ‘1’.
    • Set the mode bit field [3:2] to the setting matching the intended synchronization method used in your system. For example, if your system uses an external device connected to the External ToD bus (1PPS input and second’s value serial input) the mode field 0x1.
    • Finally enable (set to ‘1’) the appropriate bits of the Port Timer enable bitfield [19:4] to enable the port TX and RX Timers.
  3. If the System Timer’s initial value is to be set by the SW through register programming, an alternative to the external ToD bus interface, then write appropriate initial values to SW loading registers: TOD_SW_SEC_0/1, TOD_SW_NS, TOD_SW_CTIME_0/1. Also, configure any static offset to be loaded by writing the TOD_SEC_SYS_OFFSET_0/1 and TOD_NS_SYS_OFFSET_0 registers.
  4. If the SW registers were updated in step 2, then a write of ‘1’ to the appropriate bits of TOD_SW_LOAD[1:0] triggers the System Timer to load the SW values.
  5. Program the Port TX/RX Timer. This includes the period values and any required static offset to the appropriate values by writing to the Port timer’s registers: TX<M>_PERIOD_0/1, RX<M>_PERIOD_0/1, and TX<M>/RX<M>_SYS_OFFSET.