GT Quad Integration with Xilinx IP Cores - 1.5 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

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Xilinx® GT-based IP cores such as Aurora, PCIe, 40G/50G Ethernet, MRMAC, and DCMAC provide Block Automation in IP integrator to enable you to connect multiple Xilinx parent IP cores to GT Quad IP cores seamlessly. IP Block Automation instantiates GT Quad IP cores and creates datapath and clock connections (USRCLK and GT REFCLK).

Perform the following steps to connect the MRMAC instance using Block Automation:

  1. Add the MRMAC instance using the Add IP option in the IP integrator canvas.
  2. Configure the MRMAC instance.
  3. Click Run_Block_Automation. In the Block Automation screen, select one of the options Auto, Start_with_New_Quad, or Customized_Connections.
  4. Perform steps 2 and 3 to add more MRMAC instances based on your system requirements.
Note: For Customized_Connections options, a GT Quad needs to be manually added to the BD design first to allow you to select lanes.

GT Quad IP core parameters are propagated from any connected IP cores when the design is validated. Therefore all GT Quad parameters are marked Auto in the Transceiver Wizard configuration screen. However, you can change the Auto option to Manual for the transceiver configuration, as shown in the following figure, to fine tune parameters such as insertion loss, drive strength, equalization, and other advanced settings. After toggling to Manual mode, any changes to the parent IP configuration followed by validation, no longer propagate GT Quad parameters from the parent IP core to the GT Quad IP core. Manual changes should only be performed after all essential parent IP core parameters are propagated to the GT Quad IP core.

Figure 1. Auto to Manual Options Switch in Transceiver Wizard