Port AXI4-Stream Clocking Modes - 1.5 English

To allow flexibility in the potential dynamic rate switching of ports, the MRMAC has two AXI4-Stream bus clock inputs to the MRMAC per direction (TX and RX), tx_axi_clk[2,0] and rx_axi_clk[2,0]. The tx_axi_clk[0] and rx_axi_clk[0] pins are used to clock ports 0 and 1. The tx_axi_clk[2] and rx_axi_clk[2] are used to clock ports 2 and 3.

The MRMAC uses the rx_axi_clk and tx_axi_clk to output some latency critical status signals, thus the IP block requires that the rx_axi_clk and tx_axi_clk inputs be driven by valid clocks regardless of the AXI4-Stream operating mode. The section for the independent AXI clocking mode describes the acceptable rx_axi_clk and tx_axi_clk.

In Flexible interface mode, it is necessary to provide tx_axi_clk and rx_axi_clk clocks to enable operation of certain high-performance device statistics and alarms, such as real-time FEC alarms.

The AXI4-Stream user interface can be configured to operate in one of two clocking modes, depending on system latency and performance requirements. As reflected in Table 1, the desired clock mode is selected using the ctl_axis_cfg_<N> field of the port MODE_REG register.