Timestamp Ports - 1.5 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)
Document ID
PG314
Release Date
2022-01-10
Version
1.5 English
Table 1. Timestamp Control Signal Descriptions (TX/RX)
Port Name I/O Clock Domain Description
ctl_rx_ptp_systemtimer[54:0],

ctl_tx_ptp_systemtimer[54:0]

 I rx/tx_ts_clk System timer input in units of 2-8 nanoseconds (unsigned). This field maps to Bits[62:8] of the correction field format in IEEE 1588-2008 (with the bottom 8 bits set to 0).

These inputs are captured on the rx_ts_clk/tx_ts_clk clock domain. It should be stable for several clock period (~10 ns) after the ctl_rx/tx_ptp_st_sync transition.
ctl_rx_ptp_st_sync,

ctl_tx_ptp_st_sync

 I rx/tx_ts_clk Transition indicates point at which ctl_rx/tx_ptp_systemtimer is valid. A DDR phase detector is used on this signal for additional phase compensation. Transitions need to be a minimum of 10 clock cycles apart. The typical delay between each pulse is 64 ns.
ctl_rx_ptp_st_overwrite,

ctl_tx_ptp_st_overwrite

 I rx/tx_ts_clk When asserted, the PTP Timer is overwritten with the ctl_rx/tx_ptp_systemtimer value if the difference is greater than the threshold amount. The overwrite occurs at the next transition of ctl_rx/tx_ptp_st_sync.
ctl_rx_ptp_st_adjust[31:0],

ctl_tx_ptp_st_adjust[31:0]

 I rx/tx_ts_clk When a bit of ctl_st_adjust_vld (defined below) is asserted, the system timer has the correction in ctl_ptp_st_adjust applied.
Note: The correction factor should be in 2's complement form. The correction is applied immediately. The unit of the value on this signal is determined by the adjustment type defined below.
ctl_rx_ptp_st_adjust_type[1:0],

ctl_tx_ptp_st_adjust_type[1:0]

 I rx/tx_ts_clk Specifies the desired adjustment using the value in ctl_ptp_st_adjust:
  • 2’b00: Adjust system timer; signed, in units of 2-8 nanoseconds (the upper 14 bits are ignored).
CAUTION:
No overflow protection is available.
  • 2’b01: Set the automatic increment value; ctl_ptp_st_adjust value is unsigned, in units of 2-8 ns (upper 14 bits ignored). This also clears any existing increment value below 2-8 ns (previously set by default or through adjustments). Increments every cycle (Nominal values - non-KP4 : 1.551515 ns; KP4 : 1.50588235 ns)
  • 2’b10: Adjust automatic increment value; signed, in units of 2-40 ns
  • 2’b11: Unused.
ctl_rx_ptp_st_adjust_vld,

ctl_tx_ptp_st_adjust_vld

 I rx/tx_ts_clk Transition of this signal triggers adjustment type defined in ctl_rx/tx_ptp_st_adjust_type with a value in ctl_rx/tx_ptp_st_adjust.
stat_rx_ptp_st_sync,

stat_tx_ptp_st_sync

 O tx/rx_axi_clk Reflects ctl_rx/tx_ptp_st_sync after it has been re-sampled to the RX/TX clock domain.
stat_rx_ptp_systemtimer[54:0],

stat_tx_ptp_systemtimer[54:0]

 O tx/rx_axi_clk PTP Timer output in units of 2-8 ns.
Note: Due to retiming, this value should be captured at least four ts_clk cycles after the stat_rx/tx_ptp_st_sync edge. Also, Bit[54] is dropped and replaced with a capture edge indicator. You can use this information to adjust the system timer value by an additional half rx_serdes_clk/tx_core_clock period.
stat_rx_ptp_st_in_range,

stat_tx_ptp_st_in_range

 O tx/rx_axi_clk Reserved, leave disconnected.