IP Facts - 1.5 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
Release Date
1.5 English
Subsystem IP Facts Table
Subsystem Specifics
Supported Device Family (1) Versal® architecture
Supported User Interfaces AXI4-Stream, AXI4-Lite
Resources N/A
Provided with Subsystem
Design Files Encrypted RTL
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx Design Constraints (XDC)
Simulation Model Verilog
Supported S/W Driver Linux Kernal. The drivers for 10G and 25GE are available here.
Tested Design Flows (2)
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Synopsys or Vivado synthesis
Release Notes and Known Issues Master Answer Record: 75817
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.