GT Quad Transceiver (SerDes) Modes - 1.5 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2022-01-10
Version
1.5 English

The MRMAC is capable of interfacing with the Xilinx® Versal® GTY transceivers through the programmable logic region. Each GT Quad lane has a dedicated transceiver interface on the MRMAC IP subsystem.

The MRMAC has PCS/PMA lane logic functions including gearbox, scrambling, lane alignment, and lane deskew. For this reason, the transceivers connected to the MRMAC must be configured to operate in RAW mode. The default transceiver lane interface configuration is 16b RAW interface for 10.3125 Gb/s lane logic, 40b RAW interface for 25.78/26.56 Gb/s lane logic, and 80b RAW interface for 53.125 Gb/s lane logic.

For multi-lane PMD lane data rates (such as 100GE or 40GE), the MRMAC GT Quad interface can support per-lane GT Quad recovered clocks in the RX direction. This option reduces transceiver latency and improves 1588 timestamping accuracy at the cost of requiring per-lane FPGA clocking resources.

For designs desiring to reduce the clocking resources consumed by the MRMAC link, the IP also supports having the transceivers configured with per-lane deskew buffering enabled, allowing all RX PMD lanes to share a common master lane clock.

The following table shows a list of all the MRMAC supported interface options for GTY transceivers including the associated line rates, GT datapath width, clock frequency, and the corresponding ctl_serdes_width field setting. The ctl_serdes_width setting is found in the MODE_REG register for each port.

Table 1. GT Quad Operating Modes
MRMAC Operating Mode GT Lane Line Rate (Gb/s) GT Interface Data Width (bits) GT Interface Clock (MHz) ctl_serdes_width[2:0]
10GE 10.3125 16 644.5313 b000
10GE Wide 10.3125 32 322.2656 b100
25GE 25.78125 40 644.5313 b010
25GE Wide 25.78125 80 322.2656 b110
40GE

XLAUI-4

10.3125 16 644.5313 b000
40GE

XLAUI-4 Wide

10.3125 32 322.2656 b100
50GE

50GAUI-2 (KP4 FEC)

26.5625 40 664.0625 b010
50GE

LAUI-2 Consortium

25.78125 40 644.5313
50GE

50GAUI-2 (KP4 FEC)

Wide

26.5625 80 332.0312 b110
50GE

LAUI-2 Consortium

Wide

25.78125 80 322.2656
100GE

100GAUI-4 (KP4 FEC)

26.5625 40 664.0625 b010
100GE

CAUI-4

25.78125 40 644.5313 b010
100GE

100GAUI-4 (KP4 FEC)

Wide

26.5625 80 332.0312 b110
100GE

CAUI-4 Wide

25.78125 80 322.2656
100GE

CAUI-4 (Overclocking)

Wide

28.21 80 352.625
FC32 Single Lane 28.05 80 350.625 b110
  1. 100GE overclocking and FC32 modes are only supported on -2LP and higher performance speed grades.
  2. The transceiver interface is re-used when the MRMAC is operating in FEC-only mode. In that mode, the MRMAC TX path performs only the FEC encode function. The output is not necessarily directly bound for a GT transceiver. Similarly, the MRMAC RX path performs only the FEC decode function and the input is not necessarily directly arriving from a GT transceiver.