This section describes the flexible interface (Flex I/F) signals. The following tables define the signal description section, the direction, and meaning of the various signals. The subsequent sections describes how the signals are hooked up for the various client rates.
| Port Name | I/O | Description |
|---|---|---|
| tx_flexif_clk[3:0] | I | Clock for the corresponding slice TX Flex Interface. The clock frequency must be the 50% of the corresponding tx_core_clk frequency for that slice. |
| tx_flexif_data(0-7)[65:0] | I | 66-bit data retrieved from the datapath. |
| tx_flex_ena_(0-3) | I | Enable signal, indicating that the corresponding tx_flexif_data word is valid. |
| tx_flex_stall_(0-3) | O | Backpressure signal (for the corresponding TX Flex Interface slice) from the MRMAC TX PHY to the user logic. User logic must provide a corresponding gap in the data after exactly 3 clock cycles. |
| tx_flexe_almarker(0-7) | I | Indicates that the corresponding tx_flexif_data(0-7) contains an alignment maker and that the scrambler (if active) should not scramble the datapath. AMs should be left unscrambled. |
| stat_tx_flexif_err_(0-3) | O | Indicates that an |E| codeword was detected on the corresponding slice of the TX Flex Interface. |
| fec_tx_din_valid_(0-3) | I | TX FEC Data Input Valid |
| fec_tx_din_start_(0-3) | I | TX FEC Data Input Start |
| fec_tx_din_is_am_(0-3) | I | TX FEC Data Input AM |
| Port Name | I/O | Description |
|---|---|---|
| rx_flex_data(0-7)[65:0] | O | 66-bit data from the RX PHY. |
| rx_flex_ena_(0-3) | O | Indicates that the corresponding rx_flex_data(0-7) is valid. The data words corresponding to rx_flex_ena_(0-3) depend on the configured mode. For more details on signaling, see the related information below. |
| rx_flex_lane0 | O | Indication that the rx_flex_data0 bus contains PCS Lane 0’s data. |
| rx_flex_almarker(0-7) | O | Indication that the data on the corresponding rx_flex_data(0-7) bus contains an Alignment Marker. For modes that do not contain alignment markers, this indicates the first cycle after the alignment marker location. |
| rx_flex_bip8(0-7) | O | Indicates that the corresponding rx_flex_data(0-7) contains a BIP8 field. |
| fec_rx_dout_valid_(0-3) | O | RX FEC Data Output Valid |
| fec_rx_dout_start_(0-3) | O | RX FEC Data Output Start |
| fec_rx_dout_flags_(0-3) | O | RX FEC Data Output Flags |
| fec_rx_dout_is_am_(0-3) | O | RX FEC Data Output AM |
| stat_rx_local_fault_(0-3) | O | Indicates PCS logic (on the corresponding slice of the RX Flex Interface) is in local fault state. |
| stat_rx_internal_local_fault_(0-3) | O | Indicates PCS logic (on the corresponding slice of the RX Flex Interface) is in local fault due to internal issue such as reset or loss of alignment. |
| stat_rx_test_pattern_mismatch_(0-3) | O | Indicates PCS logic (on the corresponding slice of the RX Flex Interface) received test pattern mismatch when configured in PCS test_pattern mode. |
| stat_rx_valid_ctrl_code | O | Indicates that PCS decoder has seen a valid control code. Allows you to monitor for valid Ethernet datastream. |
| stat_rx_pcs_bad_code | O | Indicates that PCS decoder received a malformed 66b code word, or improper code word, and transitioned to the E state. |
| stat_rx_hi_ber | O | Indicates that the PCS is in the High BER state as identified by IEEE 802.3 CL82 (100/50/40GE) or CL49 (10/25GE). |
| stat_rx_status | O | Indicates that the Port is out of fault and not in the HI BER state. |
| stat_rx_flexif_err | O | Indicates that a Flex I/F Error has occurred and the data and flags on the RX Flex I/F is in error. The port’s RX datapath should be reset. |
Each port of the Flex I/F is reset along with the overall port logic by the assertion of
the appropriate tx_core_reset[3:0] and rx_core_reset[3:0]
pins. The TX direction is reset by the toggling of the tx_core_reset and RX
logic by the toggling of that port’s rx_core_reset pin. Asserting reset on
a port’s rx_core_reset pin alters both the PCS and the Client Monitoring
functions of the Flex I/F.