时钟相移信息在“Clock Report”(时钟报告)(report_clocks
命令)中提供。当 MMCM/PLL 时钟发生相移且 MMCM/PLL 的 PHASESHIFT_MODE
属性设置为 LATENCY
时,自动衍生时钟以 S 属性(时延模式下的管脚相移)来标记。此外,时钟报告的 Generated Clocks
部分下的时钟详情可显示 MMCM/PLL 插入延迟中计入的管脚相移量。
注释: 报告中仅含对应于自动衍生时钟相移的延迟。在自动衍生时钟波形定义中不包含来自 MMCM/PLL 块的相移量。
在以下示例中,MMCM 的 PHASESHIFT_MODE 属性设置为 LATENCY。自动衍生时钟 clk_out1_clk_wiz_0
并未给 MMCM 管脚 CLKOUT0
定义相移,但时钟 clk_out2_clk_wiz_0
已为 MMCM 管脚 CLKOUT2
定义 -90 度相移。
Attributes
P: Propagated
G: Generated
A: Auto-derived
R: Renamed
V: Virtual
I: Inverted
S: Pin phase-shifted with Latency mode
Clock Period(ns) Waveform(ns) Attributes Sources
clk_in1 10.000 {0.000 5.000} P {clk_in1}
clk_out1_clk_wiz_0 10.000 {0.000 5.000} P,G,A {clknetwork/inst/mmcme3_adv_inst/CLKOUT0}
clk_out2_clk_wiz_0 10.000 {0.000 5.000} P,G,A,S {clknetwork/inst/mmcme3_adv_inst/CLKOUT2}
====================================================
Generated Clocks
====================================================
Generated Clock : clk_out1_clk_wiz_0
Master Source : clknetwork/inst/mmcme3_adv_inst/CLKIN1
Master Clock : clk_in1
Multiply By : 1
Generated Sources : {clknetwork/inst/mmcme3_adv_inst/CLKOUT0}
Generated Clock : clk_out2_clk_wiz_0
Master Source : clknetwork/inst/mmcme3_adv_inst/CLKIN1
Master Clock : clk_in1
Multiply By : 1
Pin Phase Shift(ns) : -2.5 (-90 degrees)
Generated Sources : {clknetwork/inst/mmcme3_adv_inst/CLKOUT2}