To create design for hard block
planning, complete the following steps
- Create a project that targets an AMD Versal™
adaptive SoC. In this lab you create a
PCIe®
design that targets xcvc1902-vsvd1760-1LP-i-L. Ensure that the
Do not specify sources at this
time option is checked while creating an RTL
project.
- Once the project loads, click the +
button in the BD canvas to add Versal
Adaptive SoC Integrated Block for PCI Express IP.
- After adding the IP onto the BD canvas, click the Run Block Automation ribbon that appears above
the BD canvas.
- Running the block automation instantiates a
pcie_versal_0_supportblock. This block contains the GT module that the PCIe® requires to talk to the external world.
- Once the block automation completes, click the Generate Block Design option under
IP INTEGRATOR menu
of the Flow Navigator
window. When a subsequent prompt appears, leave the settings at default and
click the Generate button.
- Create a top-level HDL wrapper before synthesizing the
design.
- The next step is to synthesize the design and open the
synthesized design. Hard Block
Planner option in Windows menu appears only once you open synthesized
design.
- Once you open a synthesized design, the Hard Block Planner reads
and processes netlist objects and collects all hard-IPs available in a design.
This planner allows you to cross-probe the location in device window view for
changing or assigning the Site.