Using the Hard Block Planner - 2024.2 English - UG899

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)
Document ID
UG899
Release Date
2024-11-13
Version
2024.2 English
To create design for hard block planning, complete the following steps
  1. Create a project that targets an AMD Versal™ adaptive SoC. In this lab you create a PCIe® design that targets xcvc1902-vsvd1760-1LP-i-L. Ensure that the Do not specify sources at this time option is checked while creating an RTL project.

  2. Once the project loads, click the + button in the BD canvas to add Versal Adaptive SoC Integrated Block for PCI Express IP.

  3. After adding the IP onto the BD canvas, click the Run Block Automation ribbon that appears above the BD canvas.

  4. Running the block automation instantiates a pcie_versal_0_support block. This block contains the GT module that the PCIe® requires to talk to the external world.

  5. Once the block automation completes, click the Generate Block Design option under IP INTEGRATOR menu of the Flow Navigator window. When a subsequent prompt appears, leave the settings at default and click the Generate button.



  6. Create a top-level HDL wrapper before synthesizing the design.

  7. The next step is to synthesize the design and open the synthesized design. Hard Block Planner option in Windows menu appears only once you open synthesized design.

  8. Once you open a synthesized design, the Hard Block Planner reads and processes netlist objects and collects all hard-IPs available in a design. This planner allows you to cross-probe the location in device window view for changing or assigning the Site.

  9. In your current design, you have two hard-IPs (PCIE40E5 and GTYE5_QUAD) whose location can be planned using the Hard Block Planner tool. You can do so by selecting the drop-down menu under the Site column and picking a suitable site from the list.
    Note: The site for the PCI Express hard IP is pre-determined by the PCI Express IP in IP integrator.

  10. For GT_QUADs, you can also plan the REFCLK source placement using the REFCLK Source column.

  11. Select the PCIe® Hard-IP group in the Hard Block Planner window. The Show Hard-IP Connectivity for Selected IP-Groups option becomes available. Select that icon to mark the Hard-IPs in that group in blue, the associated GTs in red and the REFCLK sources in green.