Validating I/O and Clock Planning - 2024.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2024-05-30
Version
2024.1 English

After performing I/O and clock planning, validate your design to ensure that it meets the design requirements. The AMD Vivado™ tools allow you to run DRCs to check for violations and perform SSN analysis to estimate switching noise levels. To perform a final validation on your I/O and clock assignments, you must implement the design and generate a bitstream.