Manually Assigning Signal Groups - 2024.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2024-05-30
Version
2024.1 English
To manually assign signal groups to byte lanes:
  1. In the Mem Byte Group column in the following figure, click the drop-down list next to a bank.

  2. Select a signal group to assign.

After each assignment, the Vivado tools run active DRCs. DRC violations appear in red, and you can click the more info link for details. The Vivado IDE shows signal groups for each Memory IP in the design, so you can plan I/O assignments for multiple memory controllers at the same time.