AMD Adaptive Computing documentation is organized around a set of standard design processes to help you find relevant content for your current development task. You can access the AMD Versal™ adaptive SoC design processes on the Design Hubs page. You can also use the Design Flow Assistant to better understand the design flows and find content that is specific to your intended design needs. This document covers the following design processes:
- System and Solution Planning
- Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine.
The following table summarizes various interface speed options available in each architecture for easy document navigation. The bit-rates mentioned in the table are based on hardware characterization using LVDS in speed grade –3 devices.
| Device Architecture | Additional Considerations | Relevant Links |
|---|---|---|
| 7 series |
HRIO (Low Speed I/O)
|
|
| AMD UltraScale™ /AMD UltraScale+™ |
Component Mode (Low Speed
I/O)
|
|
Native Mode (High Speed I/O)
|
||
| AMD Versal™ adaptive SoC |
I/O Logic (Low Speed I/O)
|
|
XPIO and X5IO (High Speed
I/O)
|