Navigating Content by Design Process - 2024.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2024-05-30
Version
2024.1 English

AMD Adaptive Computing documentation is organized around a set of standard design processes to help you find relevant content for your current development task. You can access the AMD Versal™ adaptive SoC design processes on the Design Hubs page. You can also use the Design Flow Assistant to better understand the design flows and find content that is specific to your intended design needs.

System and Solution Planning
Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine.

The following table summarizes various interface speed options available in each architecture for easy document navigation. The bit-rates mentioned in the table are based on hardware characterization using LVDS in speed grade –3 devices.

Table 1. Navigating IP and Clock Planning Content
Device Architecture Additional Considerations Relevant Links
7 series HRIO (Low Speed I/O)
  • Bit-rate range 0 to 1250 Mb/s
HPIO (High Speed I/O)
  • Bit-rate range 0 to 1600 Mb/s
AMD UltraScale™ /AMD UltraScale+™ Component Mode (Low Speed I/O)
  • Bit-rate range for AMD UltraScale™ HP/HR bank or AMD UltraScale+™ HP bank 0-1250 Mb/s
  • Bit-rate range for AMD UltraScale+™ HD bank 0-250 Mb/s
Native Mode (High Speed I/O)
  • Bit-rate range 300 to 1600 Mb/s (only HP banks)
AMD Versal™ adaptive SoC I/O Logic (Low Speed I/O)
  • Bit-rate range 0-300 Mb/s (Both HD and XP banks)
XPIO (High Speed I/O)
  • Bit-rate range 200-1800 Mb/s (Only XP banks)