Placing Gigabit Transceiver I/O Ports - 2024.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2024-05-30
Version
2024.1 English

To better manage GTs, the I/O planning windows group the two related I/O diff pairs and the GT logic object automatically during selection, placement, and moving. The GT objects are selected as one object and move together, which prohibits illegal assignment of the GT resources.

If the interactive DRCs are enabled, the noise sensitive I/O pins surrounding the GTXs are prohibited automatically during port placement. For more information, see Enabling or Disabling Interactive DRCs.

For information about transceiver placement rules, see the following, depending on your device.
  • 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
  • UltraScale Architecture GTH Transceivers User Guide (UG576)
Tip: When placing gigabit ports for 7 series, UltraScale, and UltraScale+, place them sequentially by right-clicking the ports that need to be placed, selecting Place I/O Sequentially, and then moving the mouse over the ports in the Package window.