Consolidated I/O Planning - 2024.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2024-05-30
Version
2024.1 English

In previous Vivado Design Suite releases, you made all I/O assignments as a part of customizing the IP. The tools stored the resulting constraints with the IP in a read-only XDC file. This required you to re-customize the IP to modify the port assignments. In addition, these constraints were not necessarily visible during I/O assignment and validation for the rest of the design. Starting in the 2015.1 releases, you can perform memory I/O assignment in the main Vivado IDE I/O Planning view layout along with the rest of the design ports. It is no longer a part of Memory IP configuration. This tool is called the Advanced I/O Planner and now includes XPIO SelectIO™ interfaces. It places all the I/O at once to optimize I/O placement and packing.

The new Memory I/O methodology enables you to:

  • Make changes to memory I/O ports without regenerating Memory IP.
  • Target Memory IP to different devices with different pinouts without regenerating Memory IP.
  • Perform I/O planning with multiple memory controllers concurrently in one environment.
  • Define and store memory port assignments in the top-level XDC constraints file for the design rather than in a read-only file within the IP.
  • Directly edit or replace the XDC constraint file or files to modify memory I/O port assignments.