The two primary types of I/O in Versal adaptive SoCs are high-performance XPIO or X5IO and high density HDIO. The XPIO includes dedicated logic to support high-speed interfaces with voltage ranges between 1.0 V and 1.5 V. HDIO, and X5IO has ranges between 1.0v and 1.2v. XPIO and HDIO banks do not have overlapping voltages or I/O standards. The HDIO supports interfaces with voltages ranging from 1.8 V to 3.3 V. The HDIO provides logic for both single data rate (SDR) and double data rate (DDR) interfaces at reduced clocking speeds. See Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) for architecture information and Vivado Design Suite Properties Reference Guide (UG912) for detailed information on Advanced IO Wizard/Advanced IO Planner.
INTERNAL_VREF). Each Versal device contains 54 pin banks for XPIO and 32 pin
banks for X5IO that can implement both single-ended and differential I/O standards. XPIO
banks support the highest speed interfaces powered at or below 1.5v, while X5IO banks
support 1.2v. Some Versal devices contain HDIO banks
that can interface with voltage levels between 1.8 V and 3.3 V. The HDIO banks contain
22
SelectIO™
pins that can implement both
single-ended I/O standards and differential I/O standards. Every
SelectIO™
IOB resource contains input, output, and
tristate drivers. The
SelectIO™
pins can be
configured to various I/O standards, both single-ended and differential.- Single-ended I/O standards are, for example, LVCMOS, LVTTL, HSTL, SSTL, HSUL, LVSTL, and POD.
- Pseudo-differential standards are, for example, differential HSTL, POD, HSUL, LVSTL, and SSTL.
- LVDS compatible.