The XCVC1902 adaptive SoC PL I/O bank voltages on the VCK190 board are listed in the following table.
Note: The VCK190 board is shipped with
VADJ_FMC set to 1.5V by the ZU4 system controller.
| Adaptive SoC (U1) Bank | Power Supply Rail Net Name | Voltage | Description |
|---|---|---|---|
| HDIO Bank 306 | VCC1V8 | 1.8V | GPIO: PB[0:1], DIP_SW[0:3], LED[0:3]; DC_PL_GPIO[0:3]; SYSCTLR_GPIO[0:5]; UART1_TXD/RXD |
| HDIO Bank 406 | VCC3V3 | 3.3V | HDMI status/ctrl(15)IF; HDIO_UART3_TX/RX; HDIO_UART4_TX/RX |
| XPIO Bank 700 | VCC1V2_DDR4 | 1.2V | DDR4_DIMM1_DQ[32:63], CB[0:7], ADDR/CTRL; DDR4_DIMM1_CLK; Si570 U2 200 MHz |
| XPIO Bank 701 | VCC1V2_DDR4 | 1.2V | DDR4_DIMM1_DQ[24:31], ADDR/CTRL |
| XPIO Bank 702 | VCC1V2_DDR4 | 1.2V | DDR4_DIMM1_DQ[0:23], CB[0:7] |
| XPIO Bank 703 | VCC1V1_LP4 | 1.1V | LPDDR4_3_DQ[0:7, 16:23], ADDR/CTRL |
| XPIO Bank 704 | VCC1V1_LP4 | 1.1V | LPDDR4_2_DQ[0:7, 16:23]; LPDDR4_3_DQ[8:15, 24:31] |
| XPIO Bank 705 | VCC1V1_LP4 | 1.1V | LPDDR4_2_DQ[8:15, 24:31], ADDR/CTRL; Si570 U3 200 MHz |
| XPIO Bank 706 | VADJ_FMC | 1.5V | 8A34001_GPIO_[0:15]; FMCP1_LA[00:16] |
| XPIO Bank 707 | VADJ_FMC | 1.5V | FMCP1_LA[17:33]; FMCP2_LA[26:33] |
| XPIO Bank 708 | VADJ_FMC | 1.5V | FMCP2_LA[00:25] |
| XPIO Bank 709 | VCC1V1_LP4 | 1.1V | LPDDR4_1_DQ[0:7, 16:23], ADDR/CTRL |
| XPIO Bank 710 | VCC1V1_LP4 | 1.1V | LPDDR4_0_DQ[0:7, 16:23]; LPDDR4_1_DQ[8:15, 24:31] |
| XPIO Bank 711 | VCC1V1_LP4 | 1.1V | LPDDR4_0_DQ[8:15, 24:31], ADDR/CTRL; Si570 U4 200 MHz |
| PMC MIO 500 | VCCO_500 | 1.8V | SYSMON IF; PMC_MIO[0:25]_500; ISL60002 U6 1.042V VREF; J1 2x6 SYSMON PIN HDR |
| PMC MIO 501 | VCCO_501 | 1.8V | PMC_MIO[26:51] |
| LP MIO 502 | VCCO_502 | 1.8V | LPD_MIO[0:25] |