[Figure 1, callout 10]
A secure digital (SD) card connector is provided for booting and file system storage. This interface is used for the SD boot mode and supports SD2.0 and SD3.0 access.
The SDIO interface signals PMC_MIO[26:36, 51] are connected to XCVC1902 ACAP bank 501, which has its VCCO set to 3.3V. Six SD interface nets PMC_MIO[26, 29, 30:33] are passed through a Nexperia IP4856CX25 SD 3.0-compliant voltage level-translator U104 (mounted on an Aries adapter), present between the XCVC1902 ACAP and the SD card connector (J302). The Nexperia IP4856CX25 U104 device provides SD3.0 capability with SDR104 performance. The Aries adapter schematic pinout to IP4856CX25 device pinout cross-reference table is shown in the following table and also on the VCK190 schematic page for this circuit.
The Nexperia SD3.0 level shifter is mounted on an Aries adapter board (located on the bottom of the board under SD socket J302) that has the pin mapping shown in the table.
| Aries Adapter Pin Number | IP4856CX25 Pin Number | IP4856CX25 Pin Name |
|---|---|---|
| 1 | C1 | CLK_IN |
| 2 | C3 | GND |
| 3 | D3 | CD |
| 4 | D2 | CMD_H |
| 5 | E2 | CLK_FB |
| 6 | E4 | WP |
| 7 | B4 | VLDO |
| 8 | C4 | VSD_REF |
| 9 | A3 | DIR_0 |
| 10 | A4 | VSUPPLY |
| 11 | B3 | VCCA |
| 12 | A2 | DIR_CMD |
| 13 | D1 | DATA0_H |
| 14 | B2 | SEL |
| 15 | B1 | DATA3_H |
| 16 | E1 | DATA1_H |
| 17 | E3 | DIR_1_3 |
| 18 | A1 | DATA2_H |
| 19 | E5 | DATA1_SD |
| 20 | D5 | DATA0_SD |
| 21 | C5 | CLK_SD |
| 22 | D4 | CMD_SD |
| 23 | B5 | DATA3_SD |
| 24 | A5 | DATA2_SD |
| 25 | C2 | ENABLE |
Information for the SD I/O card specification can be found at the SanDisk Corporation or SD Association websites. The VCK190 SD card interface supports the SD1 (2.0) and SD2 (3.0) configuration boot modes documented in the Versal ACAP Technical Reference Manual (AM011).
For Nexperia IP4856CX25 component details, see the IP4856CX25 data sheet at the Nexperia website.
The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Xilinx Design Constraints.