The AMD Versal™ Adaptive SoC GT Controller for DisplayPort and SDI bridge IP is the supported method of configuring and using transceivers with AMD UHD-SDI and DisplayPort Subsystem IPs. The GT Controller for DisplayPort and SDI core simplifies serial transceiver (GT) use by providing a standardized interface of serial transceiver functions. The functional block diagram of the core is shown in the following figure.
The GT Controller for DisplayPort and SDI bridge IP (v_vid_gt_bridge_ip_v3_0) is available in the IP integrator canvas.
A custom design entry is created through a Bridge IP only. It instantiates, configures, and
connects single or multiple GT Wizard IPs. You can add the GT Controller for DisplayPort and SDI bridge IP (v_vid_gt_bridge_ip_v3_0) in the IP integrator and configure its parameters. IP
parameters are programmable through the GUI including number of lanes. For more information,
see IP integrator (IP integrator) Design Entry for Custom IP. The supported features in the
Bridge IP are:
- Simplex and duplex configurations.
- Multiple line rate configurations can be captured as part of IP customization.
- Up to 16 line rates can be configured per channel per direction.
- Configurable lane support for one, two, and four lanes for DisplayPort Subsystem IPs.
- Maximum line rate configuration up to 8.1 Gb/s for DisplayPort Subsystem IPs.
- RCPLL and LCPLL selection for UHD-SDI Subsystem IPs.