|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™
adaptive SoC (GTYE5 and GTYP) |
| Supported User Interfaces |
AXI4-Stream
|
| Provided with
Core
|
| Design Files |
RTL |
| Example Design |
Provided with the SDI and DisplayPort IP cores |
| Test Bench |
Not provided |
| Constraints File |
N/A |
| Simulation Model |
N/A |
| Supported S/W Driver |
N/A |
| Tested Design
Flows
2
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973)
|
| Synthesis |
Vivado Synthesis |
| Support |
| All Vivado IP Change Logs |
Master Vivado IP Change Logs:
72775
|
|
Support web
page
|
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
- See the SDI and DisplayPort documentation in References.
|