The architecture of GTYE5 consists of four PLLs in total for a QUAD, out of which two are shared with upper DUO and the remaining ones are shared with lower DUO.
When supporting multiple links of SDI on Versal devices, there are two possible use-cases listed below with independent rate control for all the SDI links.
Multilink SDIs with Independent Reference Clocks for TX and RX
To support independent reference clocks for TX and RX with independent rate control of all SDI links, separate PLL is required for each simplex, that is, two PLLs for each SDI link. As there are only two PLLs in a DUO, one link per DUO or two links in a QUAD can be supported.
However, four links can be supported, provided that all 4xRX links run only integer (at different rates) using rate grouping feature in GT Wizard. For example- Link 1 RX can be at 1.5G integer, Link 2 RX can be at 3G integer, Link 3 RX can be at 6G integer, and Link 4 RX can be at 12G integer. Nevertheless, for the same example, two links cannot be at integer and fractional.
You can select rate grouping option in GT Bridge as shown in the following figure.
In this case, to support four links with independent reference clocks, you cannot run a link in RX in integer and another link of RX in fractional rate. See the following example for supported and non-supported cases.
- Supported case
- Rx0 can be at 12G Integer
- Rx1 can be at 6G Integer
- Rx2 can be at 3G Integer
- Rx3 can be at 1.5G Integer
- Supported case
- Rx0 can be at 12G Fractional
- Rx1 can be at 6G Fractional
- Rx2 can be at 3G Fractional
- Rx3 can be at 1.5G Fractional
- Non-supported case
- Rx0 can be at 12G Integer
- Rx1 can be at 6G Fractional
- Rx2 can be at 3G Integer
- Rx3 can be at 1.5G Fractional
Multilink SDIs with Common Reference Clocks for TX and RX
To support common reference clocks for TX and RX with independent rate control of all SDI Links, use one PLL for integer and another PLL for fractional in a DUO. Use internal resources (dividers and multipliers) of GT Quad to support all SDI rates independently for each link.
By using one PLL for integer and another PLL for fractional, all four links per quad with independent control for each link can be supported. The following is an example of Simplex configuration.