DisplayPort Interface Ports - 2.0 English

Versal Adaptive SoC GT Controller for DisplayPort and SDI LogiCORE IP Product Guide (PG398)
Document ID
PG398
Release Date
2023-05-20
Version
2.0 English
Table 1. DisplayPort Transmitter Interface
Signal Name  I/O Description
tx_axi4s_ch<n>_tdata[31:0] I Video data input for lane <n>
tx_axi4s_ch<n>_tuser[11:0] I User data for lane <n>
tx_axi4s_ch<n>_tvalid I Video data input valid for lane <n>
tx_axi4s_ch<n>_tready O AXI4-Stream tready output for lane <n>
status_sb_tx_tdata[31:0] O Sideband status to DisplayPort
status_sb_tx_tvalid O Sideband status valid to DisplayPort
status_sb_tx_tready I AXI4-Stream tready input
Table 2. DisplayPort Receiver Interface
Signal Name  I/O  Description
rx_axi4s_ch<n>_tdata[31:0] O Video data output for lane <n>
rx_axi4s_ch<n>_tuser[11:0] O User data out for lane <n>
rx_axi4s_ch<n>_tvalid O Video output data valid for lane <n>
rx_axi4s_ch<n>_tready I AXI4-Stream tready output for lane <n>
control_sb_rx_tdata[7:0] I  Sideband control from DisplayPort
control_sb_rx_tvalid I Sideband control valid from DisplayPort
control_sb_rx_tready O AXI4-Stream tready
status_sb_rx_tdata[31:0] O Sideband status signal to DisplayPort
status_sb_rx_tvalid O Sideband status signal to DisplayPort
status_sb_rx_tready I Core ready