UHD-SDI Interface Ports

Table 1. UHD-SDI Transmitter Interface
Signal Name	I/O	Description
tx_axi4s_ch<n>_tdata[39:0]	I	Video data input for lane <n>
tx_axi4s_ch<n>_tvalid	I	Video data input valid for lane <n>
tx_axi4s_ch<n>_tready	O	AXI4-Stream tready output for lane <n>
sdi_ctrl_sb_tx_in[31:0]	I	TX Sideband signal information from SDI for transceiver. Bit 2-0: tx_mode Bit 3: tx_m Bit 31-4: 0
sdi_ctrl_sb_tx_in_tvalid	I	TX Sideband control valid from SDI
sdi_ctrl_sb_tx_in_tready	O	AXI4-Stream tready Input
sdi_ctrl_sb_tx_out[31:0]	O	Sideband signal information to transceiver block. Bit 2-0: tx_mode Bit 3: tx_m Bit 31-4: 0
sdi_ctrl_sb_tx_out_tvalid	O	TX Sideband control signal valid to transceiver
sdi_ctrl_sb_tx_out_tready	I	Transceiver Ready
gpi_out_tx	O	Assert when rate change happens. Connect this signal to GPI port of GT QUAD. Refer to Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) for more details.
gpo_in_tx	O	Set corresponded GPO ports in response to assertions of GPI ports. Connect this signal to GPO port of GT QUAD. Refer Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) for more details.

Table 2. UHD-SDI Receiver Interface
Signal Name	I/O	Description
rx_axi4s_ch<n>_tdat[39:0]	O	Video data output for channel <n>
rx_axi4s_ch<n>_tvalid	O	Video output data valid for channel <n>
rx_axi4s_ch<n>_tready	I	AXI4-Stream tready output for channel <n>
sdi_ctrl_sb_rx_in[31:0]	I	RX Sideband signal information from SDI. Bit 2:0: rx_mode Bit 3: rx_mode_locked Bit 4: rx_level_b_3g Bit 5: rx_ce Bit 31–6: unused
sdi_ctrl_sb_rx_in_tvalid	I	RX Sideband control signal valid to GT Bridge.
sdi_ctrl_sb_rx_in_tready	O	GT Bridge Ready.
sdi_ctrl_sb_rx_out[31:0]	O	RX Control Sideband signal information to transceiver. Bit 2:0: rx_mode Bit 3: rx_mode_locked Bit 4: rx_level_b_3g Bit 5: rx_ce Bit 31–6: unused
sdi_ctrl_sb_rx_out_tvalid	O	RX Sideband control signal valid to transceiver.
sdi_ctrl_sb_rx_out_tready	I	Transceiver Ready.

UHD-SDI Interface Ports - 2.0 English