Synthesizing and Implementing the Design - 1.1 English

Perform the following steps after the system is created:

1. Validate the design for correctness. Right-click in the IP integrator canvas and click Validate Design or press F6.
2. Add REFCLK create_clock constraint on top level XDC.
3. After the design is validated and the top-level file is generated, click Run Synthesis in Vivado to synthesize the design.
4. Open synthesized design > Layout > I/O Planning for GT and refclk pin placements as shown in the following figure:
   
   

   Alternatively, navigate to the Window Hard Block Planner pane as shown in the following figure:

   
   
   
5. Open the Package Pins tab and provide GT Quad and GT reference clock locations in the corresponding MGT banks.
6. After all the I/O Ports are assigned, click Run Implementation to implement the design.