Customizing and Generating the Core - 1.1 English

This section includes information about using AMD tools to customize and generate the core in the AMD Vivado™ Design Suite.

If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.

As mentioned in Product Specification, AMD Versal™ Adaptive SoC Transceivers Wizard solution contains two cores:

1. Versal Adaptive SoC Transceivers Bridge - A reference parent IP (Bridge IP) that configures Transceivers Wizard parameters. For more information, see IP Integrator (IPI) Design Entry for Custom IP.
2. Versal Adaptive SoC Transceivers Wizard - A wrapper around GT*_QUAD primitive. It consists of single GT Quad (GT quad base IP). Multiple Transceivers Wizards are to be instantiated for multi-lane (>4 lanes) designs. Refer to IPI Design Entry section below for the recommended design entry for custom Design entry. AMD GT parent IPs would be supporting Block automation to get the required connectivity.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

1. Select the IP from the IP catalog.
2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.