To simulate an instance of the Wizard IP core, first open its example design.
In the example project, go to in the Vivado Integrated Design Environment (IDE) to start a behavioral simulation.
See Lab 6 in Vivado Design Suite Tutorial: Logic Simulation (UG937) for GTME5 integer ports related simulation updates.
The example design simulation test bench provides the requisite free-running
clock and transceiver reference clock signals, and a reset all pulse to the example design
logic and reset controller helper block input ports. This stimulus is sufficient to enable the
helper blocks to bring up the remainder of the system. After some time, the transceiver PLL(s)
will achieve lock, allowing the reset controller helper block finite state machines to
complete the full reset sequence. After the completion of the reset sequence, you can observe
the example stimulus module transmitting data. A short time later, the example checking module
begins to search for data alignment and checks for data integrity, which is in turn used by
the link status logic to drive the link status indicator. In multi-line rate configurations,
the example design switches to the next line rate and again tries to achieve lock and other
Reset Done signals. You can observe that when *rate_sel[3:0]
ports are toggled, their corresponding *outclk values change
after *resetdone is asserted high.
The rate port should be driven with 0 until the initial tx/rx_resetdone_out_ip0 is asserted.
tx/rx_resetdone_out_ip0
is high until gtpowergood is asserted high and goes low when
ch*_tx/rxmstreset is applied to the quad. Finally, it
measures the expected user clk frequency to ensure the expected line rate is achieved. After
every rate change, it prints the following message:
