IP Facts - 1.1 English

Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331)

Document ID

PG331

Release Date

2023-10-24

Version

1.1 English

AMD LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family	AMD Versal™ Adaptive SoC
Supported User Interfaces	N/A
Resources	Versal Adaptive SoC GTM register map: Performance and Resource Use web page Versal Adaptive SoC GTY and GTYP register map: Performance and Resource Use web page
Provided with Core
Design Files	RTL
Example Design	Verilog
Test Bench	Verilog
Constraints File	Xilinx Design Constraints (XDC)
Simulation Model	Source HDL with SecureIP transceiver simulation
Supported S/W Driver	N/A
Tested Design Flows
Design Entry	AMD Vivado™ Design Suite
Simulation	For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
Synthesis	Vivado Synthesis
Support
Release Notes and Known Issues	Master Answer Record: 75716
All Vivado IP Change Logs	Master Vivado IP Change Logs: 72775
Support web page
For a complete list of supported devices, see the AMD Vivado™ IP catalog. For the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).