Example Design - 1.1 English

An example design can be generated for any customization of the Transceivers Wizard IP core. After you customize and generate a core instance, select Open IP Example Design AMD Vivado™ Integrated Design Environment (IDE) option for that instance. A separate Vivado project opens with the wizard example design as the top-level module. The example design instantiates the customized core. Example design invokes IP integrator in the background, adds gt_bridge_ip, and generates GT Quad design for a given configuration as shown in the following figure.

Figure 1. Core Example Design

The purpose of the Wizard IP example design is to:

Provide a simple demonstration of the customized core instance operating in simulation through the use of a link status indicator based on PRBS generators and checkers.
Provide a starting point for integrating the customized core into your system, including reference clock buffers.

The gt_bridge_ip contains configurable PRBS generator and checker modules per transceiver channel that enable simple data integrity testing and resulting link status reporting. The example design is also synthesizable.

Note: You need to provide an appropriate GT Quad and GTREFCLK location in IP xdc for a selected device if you are not using IO Planner for location selection.

Note: Example design is not provided for Bridge IP.

The Bridge IP has a reset controller helper block that simplifies resetting and initializing the serial transceiver primitive.