Reset Controller Helper Block - 1.1 English

Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331)

Document ID
PG331
Release Date
2023-10-24
Version
1.1 English

The Reset Controller helper block must be provided with the free running clock gtwiz_reset_clk_freerun_in that you have specified during IP customization. A single instance of the helper block is delivered with each instance of the GT Bridge IP core.

Table 1. Reset Controller Helper Block Ports
Name Direction Width Clock Domain Description
gtwiz_reset_clk_freerun_in IN 1 ASYNC Free running clock, used to reset transceiver primitives. It should be toggling before device configuration.
gtwiz_reset_all_in IN 1 ASYNC Signal to reset the phase-locked loops (PLLs) and active data directions of transceiver primitives. The falling edge of an active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in the duration initializes the process.
gtwiz_reset_tx_pll_and_datapath_in IN 1 ASYNC Signal to reset the transmit data direction and associated PLLs of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in the duration initializes the process.
gtwiz_reset_tx_datapath_in IN 1 ASYNC Signal to reset the transmit data direction of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in the duration initializes the process.
gtwiz_reset_rx_pll_and_datapath_in IN 1 ASYNC Signal to reset the receive data direction and associated PLLs of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in the duration initializes the process.
gtwiz_reset_rx_datapath_in IN 1 ASYNC Signal to reset the receive data direction of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in the duration initializes the process.
gtpowergood_in IN 1 ASYNC Connected to GTPOWERGOOD signals produced by the transceiver channel logic.
gtwiz_reset_userclk_tx_active_in IN 1 ASYNC

For GTY, GTYP: Logical AND of all TXPMARESETDONE signals produced by the transceiver channel primitives.

For GTM: Logical AND of all TXPROGDIVRESETDONE signals produced by the transceiver channel primitives.
gtwiz_reset_userclk_rx_active_in IN 1 ASYNC

For GTY, GTYP: Logical AND of all RXPMARESETDONE signals produced by the transceiver channel primitives.

For GTM: Logical AND of all RXPROGDIVRESETDONE signals produced by the transceiver channel primitives.
mst_tx_resetdone IN 1 ASYNC Logical AND of all MSTTXRESETDONE signals produced by transceiver channel primitives.
mst_tx_resetdone IN 1 ASYNC Logical AND of all MSTRXRESETDONE signals produced by the transceiver channel primitives.
mst_tx_reset OUT 1 gtwiz_reset_clk_freerun_in Active-High signal fanned out to TXMSTRESET port of transceiver channels.
mst_rx_reset OUT 1 gtwiz_reset_clk_freerun_in Active-High signal fanned out to RXMSTRESET port of transceiver channels.
mst_tx_dp_reset OUT 1 gtwiz_reset_clk_freerun_in Active-High signal fanned out to TXMSTDATAPATHRESET port of transceiver channels.
mst_rx_dp_reset OUT 1 gtwiz_reset_clk_freerun_in Active-High signal fanned out to RXMSTDATAPATHRESET port of transceiver channels.
txuserrdy_out OUT 1 gtwiz_reset_clk_freerun_in Active-High signal fanned out to TXUSERRDY port of all transceiver channel primitives.
rxuserrdy_out OUT 1 gtwiz_reset_clk_freerun_in Active-High signal fanned out to RXUSERRDY port of all transceiver channel primitives.
gtwiz_reset_tx_done_out OUT 1 gtwiz_reset_clk_freerun_in Active-High indication that the transmitter reset sequence of transceiver primitives, as initiated by the reset controller helper block, is completed.
gtwiz_reset_rx_done_out OUT 1 gtwiz_reset_clk_freerun_in Active-High indication that the receiver reset sequence of transceiver primitives, as initiated by the reset controller helper block, is completed.

The helper block follows the controller reset sequence and contains two state machines.

Transmitter Reset State Machine
Resets the transmitter PLL and/or the transmitter datapath of all transceiver primitives and indicates their completion.
Figure 1. Transmitter Reset State Machine
Receiver Reset State Machine
Resets the receiver PLL and/or the receiver datapath of all transceiver primitives and indicates their completion.
Figure 2. Receiver Reset State Machine

The gtwiz_reset_all_in input initiates both transmitter and receiver state machines. The transmitter and receiver reset state machines are independent of one another. Each can be initiated either directly through the user interface if needed or controlled by the gtwiz_reset_all_in input.

When the gtwiz_reset_all_in signal is activated, the transmitter and receiver state machines are initiated simultaneously. If the channel configuration is set up such that the receiver incoming data is dependent on the transmitter data, the receiver should go through a separate datapath reset after the gtwiz_reset_all_in has completed, or use the reset_tx_pll_and_datapath followed by reset_rx_datapath.