Product Specification - 1.1 English

Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331)
Document ID
PG331
Release Date
2023-10-24
Version
1.1 English

The AMD Versal™ Adaptive SoC Transceivers Wizard solution contains two cores:

Versal Adaptive SoC Transceivers Wizard
A wrapper around GT*_QUAD primitive. It consists of single GT Quad (gt_quad_base IP). Multiple transceivers wizards need to be instantiated for multi-lane (>4 lanes) designs.
GT Quad base IP
GT Quad base IP is available as Versal Adaptive SoC Transceivers Wizard (gt_quad_base) in the AMD Vivado™ IP catalog. It instantiates, configures, and connects a GT*_QUAD primitive and provided simulation support to showcase various GT Quad features. You can configure GT Quad base IP to share multiple protocol IPs, each supporting multiple line rates, create and simulate example design to understand dynamic line-rate switching and GT Quad sharing across multiple protocol IPs. For port list and definitions of this IP, see Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) and Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017).
Versal Adaptive SoC Transceivers Bridge
It is a reference parent IP (Bridge IP) that configures transceivers wizard parameters.
Bridge IP
Versal Adaptive SoC Transceivers Bridge IP (gt_bridge_ip) is available in the IP integrator canvas. A custom design entry is created through a Bridge IP only. Bridge IP is a configurable wrapper through which GT Quad base IPs (gt_quad_base) are configured.

Bridge IP has two operation modes:

Default Mode: Use this mode for standalone transceiver wizard simulation and validation on the FPGA board. In this mode, Bridge IP encapsulates data generator, checker logic, and reset logic based on the programmed configuration.

Pass Through Mode: When Bridge IP is configured in the Pass Through mode, it exposes all relevant signals of GT Quad to the application interface. After configuring all GT parameters, it instantiates, configures, and connects single or multiple GT Quad base IPs(gt_quad_base).

You can add Versal Adaptive SoC Transceiver Bridge IP (gt_bridge_ip) in the IP integrator and configure its parameters in the GUI, including the number of lanes and click Block Automation.
Note: gt_quad_base parameters are inherited from gt_bridge_ip.
It instantiates multiple gt_quad_base based on the number of lanes configured in gt_bridge_ip and makes all the required connections. The following figures represent systems with Bridge IPs and GT Quad base IPs that can be generated in an IP integrator canvas. Each Bridge IP can be configured for multiple line rate options in the GUI. Multiple Bridge IPs can be shared by a GT Quad base depending on the Bridge IP requirements. For more information, see IP Integrator (IPI) Design Entry for Custom IP.
Figure 1. Bridge IP in Pass Through Mode
Figure 2. Single Bridge IP - GT Quad Design
Figure 3. Multiple Bridge IPs Sharing GT Quad
The following are the supported features in the Bridge IP:
  • Simplex and Duplex configurations
    • Preset configurations for common standards
    • Full control of parameters for fine-tuning
    • Block Automation support to connect single or multiple GT Quads
  • Native support of dynamic line rate changing, without the need to reprogram or build an APB3 controller. Up to 16 line rates are configured per channel per direction

The following are the bridge IP ports in Pass Through mode:

Table 1. Bridge IP Ports in Pass Through Mode
Name Direction Width Clock Domain Description
gtreset_in Input 1 Async

The user signal to reset the phase-locked loops (PLLs) and active data directions of transceiver primitives.

An active-High, asynchronous pulse of at least one apb3clk period in the duration initializes the process.

Connected to the gtwiz_reset_all_in signal of reset controller helper block.
reset_tx_pll_and_datapath_in Input 1 Async

The user signal to reset the transmit data direction and associated PLLs of transceiver primitives.

An active-High, asynchronous pulse of at least one apb3clk period in the duration initializes the process.

Connected to the gtwiz_reset_tx_pll_and_datapath_in signal of reset controller helper block.
reset_rx_pll_and_datapath_in Input 1 Async

The user signal to reset the receive data direction and associated PLLs of transceiver primitives.

An active-High, asynchronous pulse of at least one apb3clk period in the duration initializes the process.

Connected to the gtwiz_reset_rx_pll_and_datapath_in signal of reset controller helper block.
reset_tx_datapath_in Input 1 Async

The user signal to reset the transmit data direction of transceiver primitives.

An active-High, asynchronous pulse of at least one apb3clk period in duration initializes the process.

Connected to the gtwiz_reset_tx_datapath_in signal of reset controller helper block.
reset_rx_datapath_in Input 1 Async

The user signal to reset the receive data direction of transceiver primitives.

An active-High, asynchronous pulse of at least one apb3clk period in the duration initializes the process.

Connected to the gtwiz_reset_tx_datapath_in signal of reset controller helper block.
tx_resetdone_out Output 1 apb3clk An active-High indication that the transmitter reset sequence of transceiver primitives is completed.
rx_resetdone_out Output 1 apb3clk An active-High indication that the receiver reset sequence of transceiver primitives is completed.
ch*_txdata_ext Input 128/256 TXUSRCLK The user interface for data to be transmitted by transceiver channels (128 bits for GTYE5/GTYP, 256 for GTME5).
ch*_rxdata_ext Output 128/256 RXUSRCLK The user interface for data received by transceiver channels (128 bits for GTYE5/GTYP, 256 bits for GTME5).
ch*_rxgearboxslip_ext Input 1 RXUSRCLK Connects to RXGEARBOXSLIP on transceiver primitives.
ch*_txheader_ext Input 6 TXUSRCLK Connects to TXHEADER on transceiver primitives.
ch*_txsequence_ext Input 7 TXUSRCLK Connects to TXSEQUENCE on transceiver primitives.
ch*_rxstartofseq_ext Output 2 RXUSRCLK Connects to RXSTARTOFSEQ on transceiver primitives.
ch*_rxheader_ext Output 6 RXUSRCLK Connects to RXHEADER on transceiver primitives.
ch*_rxheadervalid_ext Output 2 RXUSRCLK Connects to RXHEADERVALID on transceiver primitives.
ch*_rxdatavalid_ext Output 2 RXUSRCLK Connects to RXDATAVALID on transceiver primitives.
ch*_txctrl0_ext Input 16 TXUSRCLK Connects to TXCTRL0 on transceiver primitives.
ch*_txctrl1_ext Input 16 TXUSRCLK Connects to TXCTRL1 on transceiver primitives.
ch*_txctrl2_ext Input 16 TXUSRCLK Connects to TXCTRL2 on transceiver primitives.
ch*_rxctrl0_ext Output 16 RXUSRCLK Connects to RXCTRL0 on transceiver primitives.
ch*_rxctrl1_ext Output 16 RXUSRCLK Connects to RXCTRL1 on transceiver primitives.
ch*_rxctrl2_ext Output 8 RXUSRCLK Connects to RXCTRL2 on transceiver primitives.
ch*_rxctrl3_ext Output 8 RXUSRCLK Connects to RXCTRL3 on transceiver primitives.
ch*_rxchbondi_ext Input 5 RXUSRCLK Connects to RXCHBONDI on transceiver primitives.
ch*_rxchanbondseq_ext Output 1 RXUSRCLK Connects to RXCHANBONDSEQ on transceiver primitives.
ch*_rxchanisaligned_ext Output 1 RXUSRCLK Connects to RXCHANISALIGNED on transceiver primitives.
ch*_rxchanrealign_ext Output 1 RXUSRCLK Connects to RXCHANREALIGN on transceiver primitives.
ch*_rxchbondo_ext Output 5 RXUSRCLK Connects to RXCHBONDO on transceiver primitives.
ch*_txbufstatus_ext Output 2 TXUSRCLK Connects to TXBUFSTATUS on transceiver primitives.
ch*_rxbufstatus_ext Output 3 RXUSRCLK Connects to RXBUFSTATUS on transceiver primitives.
ch*_rxcommadet_ext Output 1 RXUSRCLK Connects to RXCOMMADET on transceiver primitives.
ch*_rxbyteisaligned_ext Output 1 RXUSRCLK Connects to RXBYTEISALIGNED on transceiver primitives.
ch*_rxbyterealign_ext Output 1 RXUSRCLK Connects to RXBYTEREALIGN on transceiver primitives.
gpio_enable Input 1 apb3clk The user signal to assert when GT REFCLK value changes during line rate switch. Assert it until *resetdone signal goes high. For more information, see gpio_enable Port Usage.
gpo_in Input 1 apb3clk Used with gpio_enable. It is auto connected during Block Automation. Drive this signal when you are not using it.
gpi_out Output 1 apb3clk Used along with gpio_enable. It is auto connected during Block Automation.
rate_sel[3:0] Input 4 apb3clk Input rate configuration port that controls the ch*_txrate[7:0] and ch*_rxrate[7:0] ports of the GT Quad. The input width 4 bits, corresponding to the number of configuration inputs (16) that can be taken at the Bridge/GT Quad IP input level.
link_status_out Output 1 apb3clk Do not care signal that can be ignored when the Pass Through mode is enabled. When the Pass Through Mode option is disabled, it indicates the link up status during example design simulation or validation. This signal is active-High when PRBS pattern of both TX and RX matches.
gt_tx_usrclk Input 1 - Connects to TXUSRCLK on the transceiver primitive.
gt_rx_usrclk Input 1 - Connects to RXUSRCLK on the transceiver primitive.
txusrclk_out Output 1 -

Transmitter clock output to be used in the user logic.

Tied internally to gt_txusrclk input of Bridge IP.
rxusrclk_out Output 1 -

Receiver clock output to be used in the user logic.

Tied internally to gt_rxusrclk input of Bridge IP.
tx_clr_out Output 1 apb3clk Active-High signal fanned out to CLR port of the BUFG_GT or MBUFG_GT primitive.
rx_clr_out Output 1 apb3clk Active-High signal fanned out to CLR port of the BUFG_GT or MBUFG_GT primitive.
tx_clrb_leaf_out Output 1 apb3clk Active-Low signal fanned out to the CLRB_LEAF port of MBUFG_GT primitive.
rx_clrb_leaf_out Output 1 apb3clk Active-Low signal fanned out to the CLRB_LEAF port of MBUFG_GT primitive.
  1. gt_lcpll_lock, gt_rpll_lock, ch_phystatus_in, and ilo_resetdone inputs can be ignored.
  2. gt_ilo_reset, gt_pll_reset, rpll_lock_out, lcpll_lock_out, pcie_rstb, and reset_mask output values are not used and can be ignored. Recommend use hsclk0_lcplllock, hsclk1_lcplllock, hsclk0_rplllock, and hsclk1_rplllock signals from respective gt_quad_base IP for monitoring purposes.
  3. Bridge IP in the Default mode contains the same set of ports listed in Table 1 except gpio_enable. These signals are handled between Bridge IP and GT Quad and are not available on Bridge IP's application interface. For more information on how the reset sequence takes place internally, see Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) and Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017).

When Bridge IP is not configured in the Pass Through mode, it contains pattern generators and checkers to support various encoding/decoding options. This is primarily used for simulation purposes. In this case, the application interface is not available for use. For example design simulation, see Example Design.

Figure 4. Bridge IP in Default Mode

Channel Bonding Ports

Channel bonding ports are not available in GT Bridge IP, but you can enable them at the Quad level using the CHANNEL_BONDING parameter.

During the IP Core generation, include the following Tcl command to the dict as part of the core generation:

set CHANNEL_BONDING true

The following are the channel bonding ports in Quad IP

Table 2. Channel Bonding Ports in Quad IP
Name Direction Width Clock Domain Description
ch*_rxchanbond_en Input 1 apb3clk Updates EB8B10B_CHAN_BOND_EN bit of CH*_RX_ELASTIC_BUF_CFG7 register
ch*_rxchanbond_master Input 1 apb3clk Updates EB8B10B_CHAN_BOND_MASTER bit of CH*_RX_ELASTIC_BUF_CFG7 register
ch*_rxchanbond_slave Input 1 apb3clk Updates EB8B10B_CHAN_BOND_SLAVE bit of CH*_RX_ELASTIC_BUF_CFG7 register
ch*_rxchanbond_level Input 3 apb3clk Updates EB8B10B_CHAN_BOND_LEVEL bits of CH*_RX_ELASTIC_BUF_CFG7 register
ch*_rxchanbond_busy Output 1 apb3clk Indicates the status of updating the channel bonding port values to register bits

For more information on master reset sequences, see Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) and Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017).