Reset State Machines - 1.1 English

The transmitter and receiver reset state machines each has two entry points:

• One, which causes the associated PLL(s) to be reset, followed by a reset of the datapath.
• Second, which only the datapath is reset.

The transmitter reset state machine initiates a PLL reset followed by a transmitter datapath reset when the gtwiz_reset_tx_pll_and_datapath_in input is pulsed. All PLLs (either LCPLL or RPLL type) instantiated by the IP instance that is used to clock the transmitter datapath are reset in response to this input. After all these PLLs lock, the transmitter programmable dividers and datapaths of all transceiver primitives are reset. If a PLL reset is not needed, a transmitter datapath-only reset is initiated when the gtwiz_reset_tx_datapath_in input is pulsed. Regardless of the reset entry point, the gtwiz_reset_tx_done_out indicator is asserted synchronous to free running clock gtwiz_reset_clk_freerun_in upon completion of the transmitter reset sequence for all transceiver primitives. Likewise, the receiver reset state machine initiates a PLL reset followed by a receiver datapath reset when the gtwiz_reset_rx_pll_and_datapath_in input is pulsed. All PLLs (either LCPLL or RPLL type) instantiated by the IP instance that is used to clock the receiver datapath are reset in response to this input. When all these PLLs lock, the receiver datapaths of all transceiver primitives are reset. If a PLL reset is not needed, a receiver datapath-only reset is initiated when the gtwiz_reset_rx_datapath_in input is pulsed. Regardless of the reset entry point, the gtwiz_reset_rx_done_out indicator is asserted synchronous to free running clock gtwiz_reset_clk_freerun_in upon completion of the receiver reset sequence for all transceiver primitives.