The following figure shows the instantiation of various modules and their hierarchy for a single core configuration of the ethernet_1_10_25g example design for a 32-bit MAC and PCS/PMA core when the GT (serial transceiver) is inside the IP core. (Serial Transceiver will always be a part of the example design for AMD Versalâ„¢ adaptive SoC).
Clocking helper blocks are used to generate the required clock frequency for the core.
The following figure shows the instantiation of various modules and their hierarchy for a single core configuration of the ethernet_1_10_25g_0 example design for a 64-bit MAC and PCS/PMA core configuration.
The following figure shows the instantiation of various modules when their hierarchy for a single core configuration of ethernet_1_10_25g_0 example design for a 32-bit PCS/PMA core.
The following user interfaces are available for different configurations.
- MAC/PCS configuration:
- AXI4-Stream for datapath interface
- AXI4-Lite for control and statistics interface
- PCS configuration:
- XGMII interface
- GMII interface
- AXI4-Lite for control and statistics interface
The
ethernet_1_10_25g_0
module is used to generate the data
packets for sanity testing. The packet generation and checking is controlled by a FSM
module.
The optional modules are described as follows:
- TX / RX pipeline register
- The TX pipeline register double synchronizes the data from the
core to the GT with respect to the
tx_clk
. The RX pipeline register double synchronizes the data from the GT to the core with respect to therx_serdes_clk
.
The following figure shows the instantiation of
various modules and their hierarchy for multiple core configuration of the
ethernet_1_10_25g_0
example design for a 32-bit PCS/PMA core.
The following figure shows the instantiation of various modules and their hierarchy for the multiple core configuration of the ethernet_1_10_25g_0 example design for a 64-bit MAC and PCS/PMA core.
The following figure shows the instantiation of various modules and their hierarchy for the multiple core configuration of the ethernet_1_10_25g_0 example design for a 32-bit PCS/PMA core.