Name | Size | I/O | Description |
---|---|---|---|
sys_reset | 1 | I | Reset for core. |
dclk | 1 | I | Stable input clk to GT. |
gt_refclk_p | 1 | I | Differential input clk to GT. Note: This port is available when the
Include GT subcore in
core option is selected in the GT Selection and
Configuration tab and the Include
Shared Logic in core option is selected in the
Shared Logic tab.
|
gt_refclk_n | 1 | I | Differential input clk to GT. Note: This port is available when the
Include GT subcore in
core option is selected in the GT Selection and
Configuration tab and the Include
Shared Logic in core option is selected in the
Shared Logic tab.
|
tx_clk_out_* | 1 | O | TX user clock output from GT. Note:
|
tx_mii_clk_* | 1 | O | TX mii clock output from GT.
Note: This
port is available when Select Core is Ethernet PCS
32-bit.
|
tx_stats_clk_out_* | 1 | O | 312.5 MHz / 125 MHz output clock to be used for the TX statistic. |
rx_stats_clk_out_* | 1 | O |
312.5 MHz / 125 MHz output clock to be used for the RX statistics. |
rx_clk_out_* | 1 | O | RX user clock output from GT. |
tx_reset_* | 1 | I | TX reset input to the core. |
user_tx_reset_* | 1 | O | TX reset output for the user logic. |
rx_reset_* | 1 | I | RX reset input to the core. |
user_rx_reset_* | 1 | O | RX reset output for the user logic. |
gtwiz_reset_tx_done_out_0 | 1 | 1 |
Tx reset done signal from the Clocking wizard in IP. Note: This port is available for Versal devices when the GT
TYPE GTM is selected from GT Selection
and Configuration tab.
|
gtwiz_reset_rx_done_out_0 | 1 | 1 |
Rx reset done signal from the Clocking wizard in IP. Note: This port is available for Versal devices when the GT
TYPE GTMis selected from GT Selection
and Configuration tab.
|
gtpowergood_out_* | 1 | O | Refer to the UltraScale Architecture GTH Transceivers User Guide UG576 for the port description. |
rxrecclkout_* | 1 | O | RX recovered clock output from GT. Note: This port is available when the
Include GT subcore in
core option is selected in the GT Selection and
Configuration tab.
|
ctl_gt_reset_all_* | 1 | O | gt_reset_all signal from the AXI4-Lite register map. Note: This port is available when the
Include AXI4-Lite is
selected from the Configuration tab and the Include Shared Logic
in example design option is selected in the Shared Logic tab
(for non-Versal device
only).
|
ctl_gt_tx_reset_* | 1 | O | gt_tx_reset signal from the AXI4-Lite register map. Note: This port is available when the
Include AXI4-Lite is
selected from the Configuration tab and the Include Shared Logic
in example design option is selected in the Shared Logic tab
(for non-Versal device
only).
|
ctl_gt_rx_reset_* | 1 | O | gt_rx_reset signal from the AXI4-Lite register map. Note: This port is available when the
Include AXI4-Lite is
selected from the Configuration tab and the Include Shared Logic
in example design option is selected in the Shared Logic tab
(for non-Versal device
only).
|
gtpowergood_in_* | 1 | I | Refer to the UltraScale
Architecture GTH Transceivers User Guide
UG576 or UltraScale Architecture GTY Transceivers User
Guide
UG578 for the port
description. Note: For Versal device only.
|
apb3clk_* | 1 | I | Refer to the or UltraScale Architecture GTY Transceivers User Guide
UG578 for the port
description. Note: For Versal device only when timestamp is
enabled.
|