| Bits | Default | Type | Signal |
|---|---|---|---|
| 15:0 | 0 | RW | an_adv_config_vector
1
Note: This register is applicable for 1G
with Clause 37 only.
|
| 30:16 | – | – | Reserved |
| 31 | 0 | RW | an_restart_config_vector |
|
|||