PCIe to DMA Address Map - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID
PG195
Release Date
2023-11-24
Version
4.1 English

Transactions that hit the PCIe to DMA space are routed to the DMA Subsystem for the PCIeDMA/Bridge Subsystem for PCI Express® internal configuration register bus. This bus supports 32 bits of address space and 32-bit read and write requests.

DMA/Bridge Subsystem for PCIe registers can be accessed from the host or from the AXI Slave interface. These registers should be used for programming the DMA and checking status.