Introduction - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID
PG195
Release Date
2024-06-05
Version
4.1 English

The AMD DMA/Bridge Subsystem for PCI Express® ( PCIe® ) implements a high performance, configurable Scatter Gather DMA for use with the PCI Express® 2.1 and 3.x Integrated Block. The IP provides a choice between an AXI4 Memory Mapped or AXI4-Stream user interface.

This IP optionally also supports a PCIe AXI Bridge mode which is enabled for only AMD UltraScale+™ devices. For details about PCIe AXI Bridge mode operation, see AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194).

This document covers DMA mode operation only.