Clocking
The axi_aclk output is the clock
used for all AXI interfaces and should drive all corresponding AXI Interconnect
aclk signals. axi_aclkis not a free running clock. This is a derived clock and will
be valid after signal axi_aresetn is
de-asserted
axi_aclk output should not be used for the system
clock for your design. The axi_aclk is not a free-run clock output.
As noted, axi_aclk may not be present at all times.Resets
For the DMA/ Bridge Subsystem for PCIe in AXI Bridge mode, there is an optional dma_bridge_resetn input pin which allows you to reset all internal
Bridge engines and registers as well as all AXI peripherals driven by axi_aresetn pin. When the following parameter is set,
dma_bridge_resetn does not need to be asserted
during initial link up operation because it will be done automatically by the IP.
You must terminate all transactions before asserting this pin. After being asserted,
the pin must be kept asserted for a minimum duration of at least equal to the
Completion Timeout value (typically 50 ms) to clear any pending transfer that may
currently be queued in the data path. To set this parameter, type the following
command at the Tcl command line:
set_property -dict [list CONFIG.soft_reset_en {true} [get_ips <ip_name>]For information about clocking and resets, see the applicable PCIe® integrated block product guide:
- 7 Series FPGAs Integrated Block for PCI Express LogiCORE IP Product Guide (PG054)
- Virtex 7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023)
- UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
- UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213)