Minimum Device Requirements - 4.1 English - PG195

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)
Document ID
PG195
Release Date
2024-12-18
Version
4.1 English
The following table lists the link widths and supported speed for a given speed grade.
Table 1. Minimum Device Requirements
Capability Link Speed Capability Link Width Supported Speed Grades
AMD UltraScale+™ Architecture (PCIE4)
Gen1/Gen2 x1, x2, x4, x8, x16 -1, -1L, -1LV, -2, -2L, -2LV, -3 1
Gen3 x1, x2, x4 -1, -1L, -1LV, -2, -2L, -2LV, -3 1
x8 -1, -2, -2L, -2LV, -3 1
x16 -1, -2, -2L, -3 1
AMD Virtex™ UltraScale+™ Devices (PCIE4C) 2
Gen1/Gen2 x1, x2, x4, x8, x16 -1, -2, -2L, -2LV, -3
Gen3 x1, x2, x4 -1, -2, -2L, -2LV, -3
x8 -1, -2, -2L, -2LV, -3
x16 -1, -2, -2L, -2LV, -3
Gen4 6 x1, x2, x4, x8 -2, -2L, -3
AMD UltraScale™ Devices
Gen1 x1, x2, x4, x8 -1, -1L, -1LV, -1H, -1HV, -2, -3 3
Gen2 x1, x2, x4, x8 -1, -1L, -1LV, -1H, -1HV, -2, -3 3
Gen3 x1, x2, x4 -1, -1L, -1LV, -1H, -1HV, -2, -3 3, 4
Gen3 x8 -2, -3
7 series Gen3 Devices
Gen1 x1, x2, x4, x8 -1, -1M, -1I, -2, -2L, -2G, -2I, -3
Gen2 x1, x2, x4, x8 -1, -1M, -1I, -2, -2L, -2G, -2I, -3
Gen3 x1, x2, x4, x8 -2, -2L, -2G, -2I, -3
7 series Gen2 Devices
Gen1 x1, x2, x4, x8 -1 5 , -2 5 , -3
Gen2 x1, x2, x4 -1 5 , -2 5 , -3
x8 -2 5 , -3
  1. -1L(0.95V), -1LV(0.90V), -2L(0.85V), -2LV(0.72V).
  2. AMD Virtex™ UltraScale+™ devices with high bandwidth memory (HBM) contain both PCIE4 and PCIE4C blocks. Only the PCIE4C blocks support Gen3 x16 in the -2LV speed grade.
  3. -1L(0.95V), -1LV(0.90V), -1H(1.0V), -1HV(0.95V).
  4. The Core Clock Frequency option must be set to 250 MHz for -1, -1LV, -1L, -1H and -1HV speed grades.
  5. Available -1 speed grades are -1M, -1I, -1Q depending on family selected. Available -2 speed grades are -2, -2G, -2I, -2IL, -2L depending on the family selected.
  6. For Gen4 mode restrictions, see UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).
Note: Subject to the documented product features and minimum device requirements, this IP supports UltraScale+ devices with one or more PCIE4 / PCIE4C integrated blocks for PCIe. Based on available programmable logic resources, the following are not supported even if this IP is supported by the device architecture:
  • AMD Artix™ UltraScale+ FPGA devices AU15P and smaller in Gen4x8 link configuration with DMA (only AXI Bridge is supported in this link configuration).
  • Contact AMD Support for information about implementing this IP in devices containing at least one integrated block for PCIe but are not supported based on available programmable logic resources.