The following features of the standard are not supported by this core:
- Tandem Configuration solutions (Tandem PROM, Tandem PCIe, Tandem with Field Updates, PR over PCIe) are not supported for AMD Virtex™ 7 XT and 7 series Gen2 devices.
- Tandem Configuration is not yet supported for Bridge mode in UltraScale+ devices.
- SR-IOV
- ECRC
- Example design not supported for all configurations.
- Narrow burst (not supported on the master interface).
- BAR translation for DMA addresses to the AXI4 Memory Mapped interface.
- This IP architecture assumes exclusive use of one or more complete GT quads, regardless of the designed link width. While it might be possible to share unused lanes in the GT quad with other instances of this IP, non-PCIe IPs, or custom GT-based interfaces for x2 and x1 link widths, AMD does not support evaluations or implementations of such sharing arrangements. The feasibility of sharing depends on the specific GT configuration required for other protocols, links, and lanes intended to share the GT quad. Factors affecting GT configuration include external REFCLKs, fabric design clocks and resets, GT clock management resources, connectivity rules, mode, and electrical settings.